Balanced sense amplifier circuits

Abstract

A balanced sense amplifier circuit. The balanced sense amplifier circuit includes a reading circuit, which includes a first transistor and a second transistor. The first and second transistors include (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The balanced sense amplifier circuit also includes a control circuit, which is electrically coupled to the first and second transistor bodies. The balanced sense amplifier circuit further includes a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. If the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

1 . A digital circuit, comprising: 
 (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively;    (b) a control circuit, which is electrically coupled to the first and second transistor bodies; and    (c) a testing circuit, which is electrically coupled to the control circuit and the enable device of the reading circuit, 
 wherein the testing circuit is capable of determining whether (i) strengths of the first and second transistors are different or (ii) the first and second transistors are of equal strength,  
 wherein, in response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first or second transistor body,  
 wherein the control circuit comprises a multiplexer,  
 wherein the multiplexer includes a first multiplexer output node and a second multiplexer output node,  
 wherein the first multiplexer output node is electrically coupled to the first transistor body, and  
 wherein the second multiplexer output node is electrically coupled to the second transistor body.  
   
   
   
       2 . The digital circuit of  claim 1 , 
 wherein the multiplexer receives as inputs a first strength adjusting voltage, a second strength adjusting voltage, and a third strength adjusting voltage, and    wherein the multiplexer is capable of applying the first strength adjusting voltage to the first or second transistor body.    
   
   
       3 . A memory device, comprising: 
 (a) a memory cell array comprising N columns, wherein N is a positive integer greater than 1;    (b) N sense amp circuits, wherein the N sense amp circuits are electrically coupled one-to-one to the N columns of the memory cell array, each of the N sense amp circuits comprising a first transistor and a second transistor, wherein the first and second transistors include: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively;    (c) N control circuits, wherein the N control circuits are electrically coupled one-to-one to the N sense amp circuits, and wherein each of the N control circuits is electrically coupled to the first and second transistor bodies of the respective sense amp circuit; and    (d) N testing circuits, wherein the N testing circuits are electrically coupled one-to-one to the N control circuits and the N sense amp circuits, 
 wherein each of the N testing circuits is capable of determining whether (i) strengths of the first and second transistors of the respective sense amp circuit are different or (ii) the first and second transistors of the respective sense amp circuit are of equal strength,  
 wherein, in response to the testing circuit determining that the strengths of the first and second transistors of the respective sense amp circuit are different, the respective control circuit is capable of adjusting the voltage of the first transistor body of the respective sense amp circuit  
 wherein each of the N control circuits comprises a multiplexer, wherein the multiplexer includes a first multiplexer output node and a second multiplexer output node,  
 wherein the first multiplexer output node is electrically coupled to the first transistor body of the respective sense amp circuit, and  
 wherein the second multiplexer output node is electrically coupled to the second transistor body of the respective sense amp circuit.