Internal voltage generator

Abstract

An internal voltage generator for stably generating an internal voltage includes a latch unit for outputting a first and a second driving signals based on a periodic signal; a first pump block for generating the internal voltage in response to the first driving signal; and a second pump block for generating the internal voltage in response to the second driving signal.

1 - 13 . (canceled)  
   
   
       14 . An internal voltage generator, comprising: 
 a charge pumping means, the charge pumping means including a first charging unit for charging a first node and a second node to a different voltage level in response to an activation of a first pumping control signal; a first pumping unit for performing a pumping operation to the first node in response to a second pumping control signal activated when the first pumping control signal is inactivated; a second charging unit for charging a third node and a fourth node to a different voltage level in response to an activation of a third pumping control signal; and a second pumping unit for performing a pumping operation to the fourth node in response to a voltage loaded on the second node, wherein a voltage loaded on the third node is outputted as an output control signal and a voltage loaded on the fourth node is outputted as an internal voltage whose voltage level is negative; and    a driving control means for generating the first to the third pumping control signals in response to a driving signal, wherein the first and the second pumping control signals have same phase and a phase of the third pumping control signal is opposite to a phase of the first pumping control signal.    
   
   
       15 . The internal voltage generator as recited in  claim 14 , wherein the first charging unit includes: 
 a first PMOS transistor whose source-drain path is connected between the external power supply voltage and the second node, wherein a gate of the first PMOS transistor receives the first pumping control signal;    a first NMOS transistor whose drain-source path is connected between the second node and the first node, wherein a gate of the first NMOS transistor receives the first pumping control signal; and    a second NMOS transistor whose drain-source path is connected between the first node and a power supply voltage, wherein a gate of the second NMOS transistor is coupled to the second node.    
   
   
       16 . The internal voltage generator as recited in  claim 14 , wherein the second charging unit includes: 
 a second PMOS transistor whose source-drain path is connected between the external power supply voltage and the third node, wherein a gate of the second PMOS transistor receives the second pumping control signal;    a third NMOS transistor whose drain-source path is connected between the third node and the fourth node, wherein a gate of the third NMOS transistor receives the second pumping control signal; and    a fourth NMOS transistor whose drain-source path is connected between the fourth node and the power supply voltage, wherein a gate of the fourth NMOS transistor is coupled to the third node.    
   
   
       17 . The internal voltage generator as recited in  claim 16 , wherein the first pumping unit includes a first capacitor whose one terminal receives the second pumping control signal and the other terminal is coupled to the first node and the second pumping unit includes a second capacitor connected between the second node and the fourth node.