Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION

Abstract

Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

1 - 17 . (canceled)  
   
   
       18 . A semiconductor structure comprising: 
 a substrate;    a layer of a dielectric material above and supported by the substrate; and    a TaN—Ta liner on the dielectric layer.    
   
   
       19 . A semiconductor structure according to  claim 18 , wherein the dielectric material is selected from the group consisting of: SiO, SiN and Si—C—O—H materials.  
   
   
       20 . A semiconductor structure according to  claim 18 , wherein the dielectric material has a dielectric constant between 1.2 and 4.0.  
   
   
       21 . A semiconductor structure according to  claim 18 , wherein: 
 the dielectric material forms a series of recesses;    the semiconductor structure further comprises a copper material deposited in said recesses and forming a series of copper wire traces;    the TaN—Ta liner is disposed between the dielectric material and said copper wire traces, and separates the copper wire traces from the dielectric material; and    the dielectric material, the copper wire traces and the TaN—Ta liner form a substantially planar top surface of the semiconductor structure.    
   
   
       22 . A semiconductor structure according to  claim 18 , wherein: 
 the dielectric material forms a series of recesses;    the semiconductor structure further comprises (i) a copper material deposited in said recesses and forming a series of copper wire traces, and (ii) a series of metal caps on said wire traces;    the TaN—Ta liner is disposed between (i) the dielectric material and (ii) the copper wire traces and the metal caps; and    the dielectric material, the copper wire traces and the TaN—Ta liner form a substantially planar top surface of the semiconductor structure.    
   
   
       23 . A semiconductor structure according to  claim 18 , wherein: 
 the dielectric material forms a series of recesses;    the semiconductor structure further comprises a copper material forming a series of copper induction coils extending into said recesses and extending upward therefrom to a level higher than the TaN—Ta liner;    the TaN—Ta liner is disposed between the copper induction coils and the dielectric material and separates the copper induction coils from the dielectric material; and    the dielectric material defines a substantially planar top surface of the semiconductor structure that is substantially free of the TaN—Ta liner.    
   
   
       24 - 31 . (canceled)