Mask rom and fabricating method thereof

Abstract

A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.

1 . A mask ROM comprising: 
 a semiconductor substrate divided into a device isolation area and an active area;    an impurity region on a prescribed portion in the active area;    a first electrode layer pattern on the semiconductor substrate to correspond to a region excluding the impurity region;    a second electrode layer pattern on the impurity region; and    a third electrode layer pattern over the semiconductor substrate including the first and second electrode patterns.    
   
   
       2 . The mask ROM of  claim 1 , wherein the second electrode layer pattern is taller than the first electrode layer pattern.  
   
   
       3 . The mask ROM of  claim 1 , further comprising an oxide layer on the second electrode layer pattern.  
   
   
       4 . The mask ROM of  claim 1 , wherein the third electrode layer pattern has a same width of the first electrode layer pattern in the region except the impurity region.  
   
   
       5 . The mask ROM of  claim 1 , further comprising a gate insulating layer inserted between the semiconductor substrate and the first electrode layer pattern.  
   
   
       6 . The mask ROM of  claim 1 , wherein the stacked first and third electrode layers play a role as a word line.  
   
   
       7 . The mask ROM of  claim 6 , further comprising an oxide layer filling a gap between the word lines.  
   
   
       8 . The mask ROM of  claim 1 , wherein the impurity region and the second electrode layer pattern works as a bit line.  
   
   
       9 . The mask ROM of  claim 1 , wherein the first to third electrode layer patterns are formed of doped polysilicon.  
   
   
       10 . The mask ROM of  claim 1 , further comprising a spacer provided to a lateral side of the first electrode layer pattern to isolate the first electrode layer pattern from the second electrode layer pattern.  
   
   
       11 .- 14 . (canceled)