Semiconductor integrated circuit device and method for desiging the same

Abstract

A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

1 - 16 . (canceled)  
   
   
       17 . A semiconductor integrated circuit device comprising: 
 a design pattern composed of a plurality of circuit elements or the wires formed on a substrate, the design pattern having a plurality of minimum size values in a spacing between parts at different potentials during standby which differ depending on an electric specification and a designing means for implementing the electric specification.    
   
   
       18 . The semiconductor integrated circuit device of  claim 17 , wherein the parts at different potentials during standby are formed in different layers.  
   
   
       19 . The semiconductor integrated circuit device of  claim 17 , wherein 
 the electric specification is suppression of a leakage current and    the designing means includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.    
   
   
       20 . The semiconductor integrated circuit device of  claim 17 , wherein 
 the electric specification is an operating speed and    the designing means includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.    
   
   
       21 . The semiconductor integrated circuit device of  claim 17 , wherein 
 the electric specification is a timing value and    the designing means includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.    
   
   
       22 . The semiconductor integrated circuit device of  claim 17 , wherein 
 the circuit elements are memory elements and    the designing means is a means for imparting a redundancy function for saving a defect.    
   
   
       23 - 41 . (canceled)  
   
   
       42 . A method for designing a semiconductor integrated circuit device, the method comprising the step of 
 forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein    the plurality of design patterns include a spacing between parts at different potentials during standby and    a plurality of design rules are applied to the plurality of design patterns depending on an electric specification of each of the design patterns and a designing method for implementing the electric specification.    
   
   
       43 . The method of  claim 42 , wherein 
 the parts at different potentials during standby are formed in different layers.    
   
   
       44 . The method of  claim 42 , wherein 
 the electric specification is suppression of a leakage current and    the designing method includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.    
   
   
       45 . The method of  claim 42 , wherein 
 the electric specification is an operating speed and    the designing method includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.    
   
   
       46 . The method of  claim 42 , wherein 
 the electric specification is a timing value and    the designing method includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.    
   
   
       47 . The method of  claim 42 , wherein 
 the circuit elements are memory elements and    the designing method is a method for imparting a redundancy function for saving a defect.    
   
   
       48 - 50 . (canceled)