US2008066860A1PendingUtilityA1

Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION

Assignee: IBMPriority: Feb 24, 2005Filed: Oct 12, 2007Published: Mar 20, 2008
Est. expiryFeb 24, 2025(expired)· nominal 20-yr term from priority
H10P 50/266H10W 72/251H10W 20/425H10W 72/012H10W 20/497H10W 20/062H10W 20/054H10W 20/037H10W 20/033H10P 50/00
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Claims

Abstract

Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Claims

exact text as granted — not AI-modified
1 - 11 . (canceled)  
   
   
       12 . A system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer, the system comprising: 
 a source of XeF2 to expose the TaN—Ta liner to XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer.    
   
   
       13 . A system according to  claim 12 , wherein said XeF2 removes said at least a portion of the TaN—Ta liner without appreciably mechanically stressing or chemically altering said dielectric material  
   
   
       14 . A system according to  claim 12 , wherein the semi-conductor structure further includes a copper layer extending above the TaN—Ta liner, and wherein: 
 the system further includes means for removing the copper to a given level, lower than the top of the TaN—Ta liner; and    said XeF2 removes enough the TaN—Ta liner to form a substantially planar top surface on the semiconductor structure.    
   
   
       15 . A system according to  claim 12 , wherein the dielectric material forms a series of recesses, copper material is deposited in said recesses to form a series of copper wire traces, and a metal cap is formed on each of the copper wire traces, said metal caps defining a top surface lower than the top surface of the TaN—Ta liner, and wherein 
 the XeF2 removes enough of the TaN—Ta liner to form a substantially coplanar top surface on the semiconductor structure.    
   
   
       16 . A system according to  claim 15 , wherein the XeF2 removes the TaN—Ta while substantially preserving the metal caps.  
   
   
       17 . A system according to  claim 12 , wherein the semiconductor structure includes a series of copper inductor coils extending to a level higher than the TaN—Ta liner, and the semiconductor structure forms a non-planar top surface, and wherein 
 the XeF2 removes the TaN—Ta liner substantially completely from on top of the dielectric material, between the copper inductor coils.    
   
   
       18 - 31 . (canceled)

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