Magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures and related methods

Abstract

A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

1 . A magnetic random access memory device comprising: 
 a memory cell access transistor on a substrate;    a bit line spaced apart from the substrate;    a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor; and    at least one magnet adjacent a sidewall of the magnetic tunnel junction structure and configured to provide a magnetic field through the magnetic tunnel junction structure.    
   
   
       2 . The device of  claim 1 , wherein a distance between the bit line and the substrate is greater than a distance between the at least one magnet and the substrate.  
   
   
       3 . The device of  claim 1 , wherein the at least one magnet is configured to provide the magnetic field along a hard magnetization axis of the magnetic tunnel junction structure.  
   
   
       4 . The device of  claim 1 , wherein the at least one magnet comprises a pair of magnets adjacent opposing sidewalls of the magnetic tunnel junction structure at opposite sides of the bit line.  
   
   
       5 . The device of  claim 1 , further comprising: 
 a controller coupled to the memory cell access transistor the bit line, and the magnetic field conductive line, wherein the controller is configured to provide a writing current through the bit line through the magnetic tunnel junction structure and through the memory cell access transistor while the at least one magnet provides the magnetic field through the magnetic tunnel junction structure.    
   
   
       6 . The device of  claim 5 , wherein the controller is configured to provide a first writing current in a first direction to reduce a resistance of the magnetic tunnel junction structure and configured to provide a second write current in a second direction opposite the first direction to increase the resistance of the magnetic tunnel junction structure.  
   
   
       7 . The device of  claim 5 , wherein the controller is further configured to provide a read current that is less than the writing current through the bit line, through the magnetic tunnel junction structure and through the memory cell access transistor, and wherein the controller is configured to determine a program status of the magnetic tunnel junction structure based on the read current.  
   
   
       8 . The device of  claim 1 , wherein the magnetic tunnel junction structure includes a pinned layer, a free layer, and an insulating layer therebetween, and wherein the at least one magnet is configured to provide the magnetic field through the free layer of the magnetic tunnel junction structure.  
   
   
       9 . The device of  claim 8 , wherein the free layer and the pinned layer comprise a same material.  
   
   
       10 . The device of  claim 8 , wherein at least one of the pinned layer and/or the free layer comprises a synthetic anti-ferromagnetic layer.  
   
   
       11 . The device of  claim 1 , wherein the at least one magnet comprises at least one permanent magnet.  
   
   
       12 . The device of  claim 1 , wherein the at least one magnet comprises at least one electromagnet.  
   
   
       11 . The device of  claim 1 , wherein the at least one magnet comprises a first magnet configured to provide a first magnetic field through the magnetic tunnel junction structure, and further comprising: 
 a second magnet on opposing sidewalls of the bit line and a surface therebetween opposite the magnetic tunnel junction structure and configured to provide a second magnetic field through the magnetic tunnel junction structure along a same direction as the first magnetic field.    
   
   
       14 . A magnetic random access memory device comprising: 
 a memory cell access transistor on a substrate;    a bit line spaced apart from the substrate;    a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor; and    a magnet on opposing sidewalls of the bit line and a surface therebetween opposite the magnetic tunnel junction structure and configured to provide a magnetic field through the magnetic tunnel junction structure.    
   
   
       15 . The device of  claim 14 , wherein the magnet is configured to provide the magnetic field along a hard magnetization axis of the magnetic tunnel junction structure.  
   
   
       16 . The device of  claim 14 , farther comprising: 
 a controller coupled to the memory cell access transistor, the bit line, and the magnetic field conductive line,    wherein the controller is configured to provide a writing current through the bit line, through the magnetic tunnel junction structure and through the memory cell access transistor while the magnet provides the magnetic field through the magnetic tunnel junction structure.    
   
   
       17 . The device of  claim 16 , wherein the controller is configured to provide a first writing current in a first direction to reduce a resistance of the magnetic tunnel junction structure and configured to provide a second write current in a second direction opposite the first direction to increase the resistance of the magnetic tunnel junction structure.  
   
   
       18 . The device of  claim 16 , wherein the controller is further configured to provide a read current that is less than the writing current through the bit line, through the magnetic tunnel junction structure and through the memory cell access transistor, and wherein the controller is configured to determine a program status of the magnetic tunnel junction structure based on the read current.  
   
   
       19 .- 22 . (canceled)  
   
   
       23 . The device of  claim 14 , wherein the magnet comprises a first magnet configured to provide a first magnetic field through the magnetic tunnel junction structure, and further comprising: 
 a pair of second magnets adjacent opposing sidewalls of the magnetic tunnel junction structure and configured to provide a second magnetic field through the magnetic tunnel junction structure along a same direction as the first magnetic field.    
   
   
       24 .- 26 . (canceled)  
   
   
       27 . A method of operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure connected between a bit line and a memory cell access transistor on a substrate, and including a magnet on opposing sidewalls of the bit line and a surface therebetween opposite the magnetic tunnel junction structure, the method comprising: 
 providing a magnetic field through the magnetic tunnel junction structure using the magnet; and    providing a writing current through the bit line, through the magnetic tunnel junction structure and through the memory cell access transistor while providing the magnetic field.    
   
   
       28 .- 29 . (canceled)