NAND Flash Memory Device and Method of Manufacturing and Operating the Same

Abstract

A NAND flash memory device, and more particularly, to NAND flash memory device and method of manufacturing operating the same as described. A dielectric film and a conduction layer are formed between cell gates so that between-cell gates are buried. Therefore, an interference effect between floating gates, which becomes profound with the level of integration increasing, and program threshold voltage distributions between cells can be improved.

1 . A method of manufacturing a NAND flash memory device, comprising: 
 defining a cell region, a source select transistor region and a drain select transistor region on a semiconductor substrate;    forming a number of stack gates in which a tunnel oxide film, a floating gate, a first dielectric film and a control gate are stacked in a predetermined region on the semiconductor substrate of the cell region, and simultaneously forming a gate oxide film and a gate in the semiconductor substrate of the source and drain select transistor regions;    performing an ion implant process to form a junction, a source and a drain in the semiconductor substrate of the cell region, and the source and drain select transistor regions;    forming a second dielectric film and a conduction layer on the entire structure, and then blanket-etching the conduction layer and the second dielectric film so that the semiconductor substrate of the source and drain select transistors is exposed;    removing the conduction layer remaining on the source and drain select transistor regions;    forming a first insulation film on the entire structure, and then etching the first insulation film so that the source is exposed, thus forming a source plug;    forming a second insulation film on the entire structure, etching the first and second insulation films so that the drain is exposed, and forming a drain plug; and    etching a predetermined region of the first and second insulation films so that the conduction layer is exposed, thus forming a plug.    
   
   
       2 . The method as claimed in  claim 1 , wherein a distance between the gates of the cell region is narrower than a distance between the gates of the source and the drain select transistor regions.  
   
   
       3 . The method as claimed in  claim 1 , wherein between the gates of the cell region are buried with the second dielectric film and the conduction layer by means of a blanket etch process.  
   
   
       4 . A method of driving a NAND flash memory device, wherein 
 a read operation of a selected block is performed by applying 0V to a selected word line, 4.5V to a non-selected word line, 4.5V to a drain select transistor and a source select transistor, respectively, 1V to a selected bit line, 0V to a non-selected bit line, 0V to a source line, 0V to a bulk and 0V to a conduction layer formed between cell gates,    a program operation of a selected block is performed by applying a program voltage of Incremental Step Pulse Programming (ISSP) method to a selected word line, 9.5V to a non-selected word line, Vcc and 0V to a drain select transistor and a source select transistor, respectively, 0V to a selected bit line, Vcc to a non-selected bit line, Vcc to a source line, 0V to a bulk and 0V to a conduction layer formed between the cell gates, and    an erase operation of a selected block is performed by applying 0V to a selected word line and a non-selected word line, respectively, making floated a drain select transistor, a source select transistor, a selected bit line, a non-selected bit line and a source line, applying 19V to a bulk and applying 0V to a conduction layer formed between the cell gates.