Semiconductor memory device comprising controllable threshold voltage dummy memory cells

Abstract

An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.

1 . A semiconductor memory device comprising: 
 a memory cell unit obtained by connecting plural memory cells,    a first select transistor provided at a first side of the memory unit    a second select transistor provided at a second side of the memory unit;    a first dummy word line provided between the memory unit and the first select transistor;    a second dummy word line provided between the memory unit and the second select transistor;    a first dummy word driver coupled to the first dummy word line; and a second dummy word driver coupled to the second dummy word line,    wherein a control signal controlling the first dummy word driver is commonly used as a control signal controlling the second dummy word driver.    
   
   
       2 . The semiconductor memory device according to  claim 1 , 
 wherein three dummy word lines including the first dummy word line are provided at the first side of the memory unit and another three word lines including the second dummy word line are provided at the second side of the memory unit.    
   
   
       3 . The semiconductor memory device according to  claim 1 , 
 wherein in the memory cell unit, plural nonvolatile memory cells are connected in parallel.    
   
   
       4 . The semiconductor memory device according to  claim 1 , 
 wherein the memory cell uses an inversion layer as a bit line in the memory cell unit.    
   
   
       5 . The semiconductor memory device according to  claim 1 , 
 wherein the memory cell unit is an NAND type EEPROM in which plural nonvolatile memory cells are connected in series.    
   
   
       6 . A semiconductor memory device comprising: 
 a memory cell unit obtained by connecting plural memory cells,    a first select transistor provided at a first side of the memory unit    a second select transistor provided at a second side of the memory unit;    a first dummy word line provided between the memory unit and the first select transistor;    a second dummy word line provided between the memory unit and the second select transistor;    a first dummy word driver coupled to the first dummy word line; and a second dummy word driver coupled to the second dummy word line,    wherein the first dummy word driver and the second dummy word driver simultaneously controls potentials of the first and second dummy word lines.    
   
   
       7 . The semiconductor memory device according to  claim 6 , 
 wherein three dummy word lines including the first dummy word line are provided at the first side of the memory unit and another three word lines including the second dummy word line are provided at the second side of the memory unit.    
   
   
       8 . The semiconductor memory device according to  claim 6 , 
 wherein in the memory cell unit, plural nonvolatile memory cells are connected in parallel.    
   
   
       9 . The semiconductor memory device according to  claim 6 , 
 wherein the memory cell uses an inversion layer as a bit line in the memory cell unit.    
   
   
       10 . The semiconductor memory device according to  claim 6 , 
 wherein the memory cell unit is an NAND type EEPROM in which plural nonvolatile memory cells are connected in series.