Small Electrode for a Chacogenide Switching Device and Method for Fabricating Same

Abstract

Semiconductor devices including a memory cell are provided. In one embodiment, the memory cell includes a first conductive material within a pore of a dielectric layer. The first conductive material may include a first surface having a first dimension that is less than the photolithographic limit. Further, in this embodiment, the memory cell includes a structure changing material in contact with the first surface of the first conductive material along a substantial portion of the first dimension. Additional devices and systems including a memory cell, and methods for manufacturing such a memory cell, are also provided.

1 . A method of manufacturing a memory cell, the method comprising: 
 forming an access device on a semiconductor substrate;    depositing a layer of dielectric material on the access device;    forming a pore in the layer of dielectric material;    depositing a first layer of conductive material within the pore to form a first electrode substantially disposed within the pore;    depositing a layer of structure changing material on the first electrode; and    depositing a second layer of conductive material on the layer of structure changing material to form a second electrode.    
     
     
         2 . The method, as set forth in  claim 1 , comprising etching the second layer of conductive material, the layer of structure changing material, the layer of dielectric material, and the access device to form a memory cell.  
     
     
         3 . The method, as set forth in  claim 1 , wherein the pore formed in the layer of dielectric material is smaller than the photolithographic limit.  
     
     
         4 . A method of manufacturing a memory cell, the method comprising: 
 forming a first conductive material within a pore of a dielectric layer, the first conductive material including a first surface having a first dimension that is less than the photolithographic limit; and    forming a layer of structure changing material in contact with the first surface of the first conductive material.    
     
     
         5 . The method of  claim 4 , wherein the first surface is within the pore of the dielectric layer.  
     
     
         6 . The method of  claim 4 , further comprising forming an access device and the dielectric layer on a semiconductor substrate such that the access device is formed between the first conductive material and the semiconductor substrate.  
     
     
         7 . The method of  claim 6 , wherein the access device includes a diode.  
     
     
         8 . The method of  claim 7 , wherein forming the access device comprises: 
 forming an n-doped material over the semiconductor substrate; and    forming a p-doped material over the n-doped material such that the p-doped material is formed between the n-doped material and the first conductive material.    
     
     
         9 . The method of  claim 4 , wherein the dielectric layer includes oxide.  
     
     
         10 . The method of  claim 4 , wherein the first dimension of the first conductive material is substantially equal to a pore dimension.  
     
     
         11 . The method of  claim 4 , wherein forming the layer of structure changing material includes forming the structure changing material in contact with the first surface of the first conductive material along essentially the entire first dimension.  
     
     
         12 . The method of  claim 11 , further comprising forming a second conductive material having a second surface in contact with the structure changing material along a second dimension, wherein the second dimension is greater than the first dimension.  
     
     
         13 . The method of  claim 4 , wherein the structure changing material includes a chalcogenide material.  
     
     
         14 . A semiconductor device, comprising: 
 a memory cell including: 
 a first conductive material within a pore of a dielectric layer, the first conductive material including a first surface having a first dimension that is less than the photolithographic limit; and  
 a structure changing material in contact with the first surface of the first conductive material along a substantial portion of the first dimension.  
   
     
     
         15 . The semiconductor device of  claim 14 , wherein the first surface is within the pore of the dielectric layer.  
     
     
         16 . The semiconductor device of  claim 14 , wherein the memory cell further includes an access device coupled between the first conductive material and a second conductive material.  
     
     
         17 . The semiconductor device of  claim 16 , wherein the second conductive material forms at least a portion of a digit line.  
     
     
         18 . The semiconductor device of  claim 16 , wherein the access device includes a diode.  
     
     
         19 . The semiconductor device of  claim 18 , wherein the diode includes: 
 a p-doped material coupled to the first conductive material; and    an n-doped material coupled to the second conductive material.    
     
     
         20 . The semiconductor device of  claim 14 , wherein the dielectric layer includes oxide.  
     
     
         21 . The semiconductor device of  claim 14 , wherein the first dimension of the first conductive material is substantially equal to a pore dimension.  
     
     
         22 . The semiconductor device of  claim 14 , further comprising a second conductive material having a second surface in contact with the structure changing material along a second dimension of the structure changing material, the second dimension being greater than the first dimension.  
     
     
         23 . The semiconductor device of  claim 14 , wherein the structure changing material includes a chalcogenide material.  
     
     
         24 . The semiconductor device of  claim 14 , wherein the structure changing material is electrically connected between the first conductive material and a word line.  
     
     
         25 . A semiconductor memory, comprising: 
 a memory matrix including a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells including: 
 a first conductive material within a pore of a dielectric layer, the first conductive material including a first surface having a first dimension that is less than the photolithographic limit; and  
 a structure changing material in contact with the first surface of the first conductive material along a substantial portion of the first dimension.  
   
     
     
         26 . The semiconductor memory of  claim 25 , further comprising peripheral circuitry including a plurality of control lines, wherein the memory matrix is coupled to at least one of the plurality of control lines.  
     
     
         27 . The semiconductor memory of  claim 26 , wherein the memory matrix is coupled to each of the control lines of the plurality of control lines and the peripheral circuitry includes addressing circuitry for addressing the memory cells contained within the memory matrix.  
     
     
         28 . The semiconductor memory of  claim 26 , wherein the memory matrix is coupled to each of the control lines of the plurality of control lines and the peripheral circuitry includes read and write circuitry for storing data in and retrieving data from the memory cells contained within the memory matrix.  
     
     
         29 . A system, comprising: 
 a microprocessor;    a memory device controlled by the microprocessor, the memory device including a memory cell comprising: 
 a first conductive material within a pore of a dielectric layer, the first conductive material including a first surface having a first dimension that is less than the photolithographic limit; and  
 a structure changing material in contact with the first surface of the first conductive material along a substantial portion of the first dimension.  
   
     
     
         30 . The system of  claim 29 , wherein the microprocessor accesses the memory device to retrieve program instructions from the memory device.  
     
     
         31 . The system of  claim 29 , wherein the microprocessor accesses the memory device to store data in the memory device and retrieve data from the memory device.  
     
     
         32 . The system of  claim 29 , wherein the structure changing material includes a chalcogenide material.  
     
     
         33 . A method of using a memory device, comprising the step of: 
 retrieving data from at least one of a plurality of memory cells contained within a memory matrix, each memory cell including: 
 a first conductive material within a pore of a dielectric layer, the first conductive material including a first surface having a first dimension that is less than the photolithographic limit; and  
 a structure changing material in contact with the first surface of the first conductive material along a substantial portion of the first dimension.  
   
     
     
         34 . The method of using the memory device of  claim 33 , wherein the memory device includes read circuitry for retrieving data from the memory cells contained within the memory matrix.  
     
     
         35 . The method of using the memory device of  claim 33 , wherein retrieving data includes retrieving program instructions.  
     
     
         36 . The method of using the memory device of  claim 33 , further including storing the data in at least one of the plurality of memory cells contained within the memory matrix.  
     
     
         37 . The method of using the memory device of  claim 36 , wherein the memory device includes write circuitry for storing the data in the at least one of the plurality of memory cells contained within the memory matrix.