Capacitor and method for fabricating the same

Abstract

A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area can increase within a limited area.

1 . A capacitor, comprising: 
 a lower electrode, constructed of a first polysilicon layer patterned in a series of ridges by implanting first conductivity type impurity ions and forming a first silicide layer stacked on an upper portion of the first polysilicon layer;    an upper electrode, constructed of a second polysilicon layer patterned in a series of ridges by implanting second conductivity type impurity ions and a second silicide layer stacked on an upper portion of the second polysilicon layer, the upper electrode being separated from the lower electrode by a predetermined interval and being engaged with the lower electrode; and    a dielectric layer separating the lower and upper electrodes.    
   
   
       2 . The capacitor according to  claim 1 , wherein the dielectric layer is a silicon nitride layer.  
   
   
       3 - 9 . (canceled)  
   
   
       10 . A capacitor, comprising: 
 a lower electrode constructed of a first polysilicon patterned in a series of ridges;    an upper electrode constructed of a second polysilicon patterned in a series of ridges, the upper electrode being are separated from the lower electrode by a predetermined interval and being engaged with the lower electrode; and    a dielectric layer separating the lower electrode and the upper electrode.    
   
   
       11 . The capacitor according to  claim 10 , wherein the first polysilicon and the second polysilicon are doped with impurity ions of opposite conductivities.  
   
   
       12 . The capacitor according to  claim 10 , the lower electrode comprising a first silicide layer stacked on the first polysilicon.  
   
   
       13 . The capacitor according to  claim 10 , the upper electrode comprising a second silicide layer stacked on the second polysilicon.  
   
   
       14 . The capacitor according to  claim 10 , wherein the dielectric layer is a silicon nitride layer.