Light sensitive display

Abstract

A light sensitive display.

1 . A light sensitive display comprising: 
 (a) said display selectively causing pixels to provide light;    (b) a plurality of light sensitive elements located within said display, wherein said light sensitive elements are transistors; and    (c) a processor that determines at least one of said plurality of light sensitive elements that experiences a change in the light level to a level less than the ambient light level.    
   
   
       2 . The display of  claim 1  wherein each of said light sensitive elements includes a first transistor that senses ambient light, and a second transistor that is inhibited from sensing ambient light with respect to said first transistor.  
   
   
       3 . A light sensitive display comprising: 
 (a) said display selectively causing pixels to provide light;    (b) a plurality of light sensitive elements located within said display suitable to sense ambient light;    (c) a processor that receives information from said light sensitive elements and determines regions of said display that experiences a change in the light level to a level less than the ambient light level and regions of said display where light in excess of said ambient light reaches said light sensitive elements.    
   
   
       4 . A liquid crystal device comprising: 
 (a) a front electrode layer;    (b) a rear electrode layer comprising a plurality of pixel electrodes;    (c) a liquid crystal material located between said front electrode layer and said rear electrode layer;    (d) a plurality of light sensitive elements located within said display wherein each of said light sensitive elements includes a first transistor that senses ambient light, a second transistor that is inhibited from sensing ambient light with respect to said first transistor; and    (e) a processor that determines at least one of said plurality of light sensitive elements that experiences a change in the light level to a level less than the ambient light level.    
   
   
       5 . The device of  claim 4  wherein a terminal of said first transistor is connected to a terminal of said second transistor with a first conductor.