High speed flip-flops and complex gates using the same

Abstract

In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.

1 . A flip-flop comprising: 
 a first PMOS transistor having a source to which a power supply voltage is connected and a gate to which a second clock signal is applied;    a second NMOS transistor having a drain to which a drain of the first PMOS transistor is connected and a gate to which input data is applied;    a third NMOS transistor having a drain to which a source of the second NMOS transistor is connected, a gate to which a clock pulse signal is applied, and a source to which a ground voltage is connected;    a first latch latching a logic level of a first node between the first PMOS transistor and the second NMOS transistor;    a fourth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected;    a fifth NMOS transistor having a drain to which a drain of the fourth PMOS transistor is connected and a gate to which the first node is connected;    a sixth NMOS transistor having a drain to which a source of the fifth NMOS transistor is connected and a gate to which the clock pulse signal is connected; and    a second latch latching a logic level of a second node between the fourth PMOS transistor and the fifth NMOS transistor.    
   
   
       2 . The flip-flop of  claim 1 , wherein: 
 the clock pulse signal is generated from a clock signal by a clock pulse generation circuit; and the clock pulse generation circuit comprises: 
 a first inverter receiving a clock signal;  
 a second inverter receiving an output of the first inverter and generating the second clock signal;  
 a third inverter receiving an output of the second inverter;  
 a NAND gate receiving the clock signal and an output of the third inverter; and  
 a fourth inverter receiving an output of the NAND gate and generating the clock pulse signal.  
   
   
   
       3 . The flip-flop of  claim 1 , wherein: 
 the clock pulse signal is generated from a clock signal by a clock pulse generation circuit; and the clock pulse generation circuit comprises: 
 a first inverter receiving a clock signal;  
 a second inverter receiving an output of the first inverter and generating the second clock signal;  
 a third inverter receiving an output of the second inverter;  
 a NAND gate receiving the clock signal, and enable signal, and an output of the third inverter; and  
 a fourth inverter receiving an output of the NAND gate and generating the clock pulse signal.  
   
   
   
       4 . The flip-flop of  claim 1 , wherein the first latch comprises: 
 a first inverter connected to the first node;    a seventh PMOS transistor having a source to which the power supply voltage is connected and a gate to which an output of the first inverter is connected;    an eighth PMOS transistor having a source to which a drain of the seventh PMOS transistor is connected, and a gate to which the clock pulse signal is connected;    a ninth NMOS transistor having a drain to which a drain of the eighth PMOS transistor is connected and a gate to which the second clock signal is connected; and    a tenth NMOS transistor having a drain to which a source of the ninth NMOS transistor is connected, a gate to which the output of the first inverter is connected, and a source to which the ground voltage is connected.    
   
   
       5 . The flip-flop of  claim 1 , wherein the first latch comprises: 
 a second inverter connected to the first node; and    a third inverter receiving an output of the second inverter and having an output connected to the first node.    
   
   
       6 . The flip-flop of  claim 1 , wherein the second latch comprises: 
 a fourth inverter connected to the second node; and    a fifth inverter receiving an output of the second inverter and having an output connected to the second node.    
   
   
       7 . A complex gate corresponding to a 2-input AND gate comprising: 
 a first PMOS transistor having a source to which a power supply voltage is connected, a gate to which a clock pulse signal is applied, and a drain to which a first node is connected;    an input portion including second and third NMOS transistors, which are serially connected to each another between the first node and a second node, wherein a gate of the second NMOS transistor is connected to first input data, and a gate of the third NMOS transistor is connected to second input data;    a fourth NMOS transistor having a drain to which the second node is connected, a gate to which the clock pulse signal is applied, and a source to which a ground voltage is connected;    a first latch latching a logic level of the first node;    a fifth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected;    a sixth NMOS transistor having a drain to which a drain of the fifth PMOS transistor is connected and a gate to which the first node is connected;    a seventh NMOS transistor having a drain to which a source of the sixth NMOS transistor is connected and a gate to which the clock pulse signal is connected; and    a second latch latching a logic level of a third node between the fifth PMOS transistor and the sixth NMOS transistor.    
   
   
       8 . A complex gate corresponding to a 3-input OR gate comprising: 
 a first PMOS transistor having a source to which a power supply voltage is connected, a gate to which a clock pulse signal is applied, and a drain to which a first node is connected;    an input portion including second through fourth NMOS transistors, which are connected in parallel to one another between the first node and a second node, wherein a gate of the second NMOS transistor is connected to first input data, a gate of the third NMOS transistor is connected to second input data, and a gate of the fourth NMOS transistor is connected to third input data;    a fifth NMOS transistor having a drain to which a source of the fourth NMOS transistor is connected, a gate to which the clock pulse signal is applied, and a source to which a ground voltage is connected;    a first latch latching a logic level of the first node between a drain of the first PMOS transistor and each of drains of the second through fourth NMOS transistor;    a sixth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected;    a seventh NMOS transistor having a drain to which a drain of the sixth PMOS transistor is connected and a gate to which the first node is connected;    a eighth NMOS transistor having a drain to which a source of the seventh NMOS transistor is connected and a gate to which the clock pulse signal is connected; and    a second latch latching a logic level of a third node between the sixth PMOS transistor and the seventh NMOS transistor.    
   
   
       9 . A complex gate corresponding to a 6-input AOI gate comprising: 
 a first PMOS transistor having a source to which a power supply voltage is connected, a gate to which a clock pulse signal is applied, and a drain to which a first node is connected;    an input portion including a cascade of second and fifth NMOS transistors, a cascade of third and sixth NMOS transistors, and a cascade of fourth and seventh NMOS transistors, which are connected in parallel to one another between the first node and a second node, wherein a gate of the second NMOS transistor is connected to first input data, a gate of the third NMOS transistor is connected to second input data, a gate of the fourth NMOS transistor is connected to third input data, a gate of the fifth NMOS transistor is connected to fourth input data, a gate of the sixth NMOS transistor is connected to fifth input data, and a gate of the seventh NMOS transistor is connected to sixth input data;    an eighth NMOS transistor having a drain to which the second node is connected, a gate to which the clock pulse signal is applied, and a source to which a ground voltage is connected;    a first latch latching a logic level of a first node between a drain of the first PMOS transistor and each of drains of the second through fourth NMOS transistors;    a ninth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected;    a tenth NMOS transistor having a drain to which a drain of the ninth PMOS transistor is connected and a gate to which the first node is connected;    an eleventh NMOS transistor having a drain to which a source of the tenth NMOS transistor is connected and a gate to which the clock pulse signal is connected; and    a second latch latching a logic level of a second node between the ninth PMOS transistor and the tenth NMOS transistor.    
   
   
       10 . The complex gate of any one of claims  7  through  9 , wherein: 
 the clock pulse signal is generated from a clock signal by a clock pulse generation circuit; and the clock pulse generation circuit comprises: 
 first, second and third inverters receiving a clock signal and being serially connected to one another;  
 a NAND gate receiving the clock signal and an output of the third inverter; and  
 a fourth inverter receiving an output of the NAND gate and generating the clock pulse signal.  
   
   
   
       11 . The complex gate of any one of claims  7  through  9 , wherein the first latch comprises: 
 a first inverter connected to the first node; and    a twelfth PMOS transistor having a source to which the power supply voltage is connected, a gate to which an output of the first inverter is connected, and a drain to which the first node is connected.    
   
   
       12 . The complex gate of any one of claims  7  through  9 , wherein the second latch comprises: 
 a second inverter receiving a signal at the third node; and    a third inverter receiving an output of the second inverter and having an output connected to the third node.