Recessed color filter array and method of forming the same

Abstract

A recessed color filter array using patterned metal as an etch stop and a method of forming the same. In one embodiment, at least one metal etch stop is formed in a semiconductor dielectric layer at the same time as the formation of one or more layers of metal interconnect elements, thereby reducing the number of necessary process steps and reducing costs. The etch stop may be formed at any layer where other metal elements are present.

1 . A method of forming a semiconductor structure comprising a substrate and a dielectric layer, said method comprising the steps of:
 forming at least one horizontal patterned metal layer in said dielectric layer, said metal layer comprising an etch stop located over a fixed array area; and   wherein the etch stop is also located over at least one interconnect for connection to electronic circuitry.   
   
   
       2 . The method of  claim 1 , further comprising the acts of
 forming a well having vertical walls in said dielectric layer over at least one pixel, said well extending through said etch stop; and   forming at least one optical element in said well allowing at least partial transmission of light between said at least one pixel and the upper vertical limit of said semiconductor structure.   
   
   
       3 . (canceled) 
   
   
       4 . The method of  claim 2 , further comprising the act of forming a metal layer over said vertical walls of said well. 
   
   
       5 . The method of  claim 2 , further comprising the formation of at least one vertical metal frame within said dielectric layer and in contact with said etch stop such that when said well is formed, said metal frame forms the vertical walls of the well. 
   
   
       6 . The method of  claim 1 , further comprising the steps of:
 forming a well having vertical walls into said dielectric layer;   forming an array of recesses through said etch stop; and   forming at least one optical element in each of said recesses.   
   
   
       7 . A semiconductor device comprising:
 a semiconductor substrate;   a dielectric layer formed over the substrate, said dielectric layer comprising:   at least one patterned metal layer comprising at least one interconnect for circuitry and an etch stop.   
   
   
       8 . The semiconductor device of  claim 7 , further comprising:
 a well having vertical walls in said dielectric layer, said well extending through said etch stop; and   at least one optical element deposed in said well for at least partial transmission of light between a pixel array and the upper vertical limit of said semiconductor structure.   
   
   
       9 . (canceled) 
   
   
       10 . (canceled) 
   
   
       11 . The device of  claim 8 , wherein said vertical walls comprise at least one vertical metal frame within said dielectric and in contact with said etch stop. 
   
   
       12 . The device of  claim 7 , further comprising:
 a well having vertical walls in said dielectric layer;   an array of recesses in said etch stop; and   at least one optical element in each of said recesses for at least partial transmission of light between a pixel array and the upper vertical limit of said semiconductor structure.   
   
   
       13 . A method of forming a semiconductor structure comprising a substrate and a dielectric layer, said method comprising the steps of:
 forming at least one horizontal patterned metal layer in said dielectric layer, said metal layer comprising an etch stop located over a fixed array area and at least one interconnect for connection to electronic circuitry;   forming a well having vertical walls in said dielectric layer, said well extending through said etch stop; and   forming at least one optical element comprising at least one color filter in said well allowing at least partial transmission of light between a pixel array and the upper vertical limit of said semiconductor structure; and   forming of at least one vertical metal frame within said dielectric layer and in contact with said etch stop such that when said well is formed, said metal frame forms the vertical walls of the well.   
   
   
       14 . A method of forming a semiconductor structure, the method comprising:
 forming a dielectric layer on a semiconductor substrate; and   forming a plurality of metal layers in the dielectric layer, the plurality of metal layers comprising at least one metal layer adapted to be an etch stop located over an array of pixels.   
   
   
       15 . The method of  claim 14 , wherein the at least one metal layer is formed on substantially a same level as one of the plurality of substantially horizontal metal layers. 
   
   
       16 . The method of  claim 14 , wherein the plurality of metal layers are formed on different levels of the dielectric layer extending from a topmost surface of the substrate to a topmost surface of the dielectric layer, and the at least one metal layer is formed on substantially a same level as one of the plurality of substantially horizontal metal layers. 
   
   
       17 . The method of  claim 16 , wherein the at least one metal layer is formed on substantially a same level as a metal layer formed in closest proximity to the topmost surface of the substrate. 
   
   
       18 . The method of  claim 16 , wherein the at least one metal layer is formed on substantially a same level as a metal layer formed in closest proximity to the topmost surface of the dielectric layer. 
   
   
       19 . The method of  claim 14 , further comprising forming a well extending through the at least one metal layer. 
   
   
       20 . The method of  claim 19 , further comprising forming a material layer within the well. 
   
   
       21 . The method of  claim 20 , wherein the material layer comprises an insulator material. 
   
   
       22 . The method of  claim 21 , wherein the insulator material is transparent. 
   
   
       23 . The method of  claim 20 , wherein the material layer has an index of refraction different from an index of refraction of the dielectric layer. 
   
   
       24 . The method of  claim 19 , further comprising forming a color filter within the well. 
   
   
       25 . The method of  claim 14 , further comprising forming multiple metal layers, each layer comprising a first portion to be used as an etch stop and a second portion to be used as an interconnect or light shield. 
   
   
       26 . A semiconductor device, comprising:
 a semiconductor substrate having an array of pixels formed therein;   a dielectric layer over the substrate; and   a plurality of metal elements formed within the dielectric layer, wherein a first metal element is formed adjacent to and on substantially a same level as a second metal element used as an interconnect, the first metal element defining a well.   
   
   
       27 . The semiconductor device of  claim 26 , wherein the well defined by the first metal element is substantially aligned with at least one pixel in the array of pixels. 
   
   
       28 . The semiconductor device of  claim 26 , wherein the plurality of metal elements comprises metal elements formed on different levels of the dielectric layer extending from a topmost surface of the substrate to a topmost surface of the dielectric layer.