Method and apparatus for reducing flicker noise in a semiconductor device

Abstract

Some embodiments discussed relate to an integrated circuit and methods for making it, comprises a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate and a gate insulator disposed on the plurality of fins and a gate stack disposed on the gate insulator and the plurality of fins are implanted by a dopant.

1 . An integrated circuit, comprising:
 a semiconductor substrate;   a plurality of fins disposed on the semiconductor substrate, wherein the plurality of fins are implanted by a dopant;   a gate insulator disposed on the plurality of fins; and   a gate stack disposed on the gate insulator.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the dopant comprises at least one of the group of materials consisting of Fluorine, Boron difluoride, Boron trifluoride, Chlorine, Hydrogen, Deuterium, Nitrogen, Argon, Xenon, Neon, and Krypton. 
     
     
         3 . The integrated circuit of  claim 2 , wherein the plurality of fins further comprises a high-k material and a supporting layer adapted to receive the dopant. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the supporting layer comprises at least one of the group of materials consisting of silicon oxide and nitrided silicon dioxide. 
     
     
         5 . The integrated circuit of  claim 2 , wherein the gate stack includes at least one of a poly silicon gate, a fully silicided gate and a metal gate. 
     
     
         6 . The integrated circuit of  claim 2 , wherein the gate insulator comprises at least one of the group of materials consisting of an oxide, a nitride, a nitrided silicon oxide and a high-k dielectric material. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the plurality of fins has a width between about 30 nm to about 3 μm. 
     
     
         8 . The integrated circuit of  claim 2 , further comprising:
 at least one of NMOS and PMOS transistors.   
     
     
         9 . The integrated circuit of  claim 2 , further comprising:
 a multi-gate FET device.   
     
     
         10 . A method of fabricating an integrated circuit, comprising:
 providing a semiconductor wafer including a plurality of fins;   oxidizing the semiconductor wafer to form a screening oxide layer on the plurality of fins;   implanting a dopant into the plurality of fins;   removing the screening oxide layer from the plurality of fins;   annealing the semiconductor wafer; and   providing a gate insulator and a gate stack disposed over the plurality of fins after the implanting of the dopant on the plurality of fins.   
     
     
         11 . The method of  claim 10 , wherein the dopant comprises at least one of the group of materials consisting of Fluorine, Boron difluoride, Boron trifluoride, Chlorine, Hydrogen, Deuterium, Nitrogen, Argon, Xenon, Neon and Krypton. 
     
     
         12 . The method of  claim 11 , wherein implanting the dopant on the plurality of fins is performed at an implantation angle that is determined by solving the equation:
   tan( a )= s/h      
       where, “s” is the spacing between two consequent fins, and “h” is the height of the silicon fins. 
     
     
         13 . The method of  claim 11 , wherein implanting the dopant on the plurality of fins is performed in a dual mode. 
     
     
         14 . The method of  claim 11 , wherein implanting the dopant on the plurality of fins is performed in a quad mode. 
     
     
         15 . The method of  claim 11 , wherein annealing the semiconductor wafer includes maintaining the semiconductor wafer at a temperature between about 950° C. and about 1200° C. for a time period between about 1 second and about 60 seconds. 
     
     
         16 . The method of  claim 11 , wherein the gate insulator includes at least one of an oxide, a nitride, nitrided silicon oxide and a high-k dielectric material. 
     
     
         17 . The method of  claim 11 , wherein implanting the dopant into the plurality of fins further comprises implanting using an implant dose less than about 6E15 atoms/cm 2  and an implant energy less than about 20 keV. 
     
     
         18 . The method of  claim 17 , further comprises cleaning of the plurality of fins using a cleaning agent. 
     
     
         19 . The method of  claim 18 , wherein the cleaning agent includes ammonia hydrogen peroxide water. 
     
     
         20 . The method of  claim 15 , wherein annealing the semiconductor wafer further comprises a post-oxidation annealing to allow distribution of the dopant into the gate insulator. 
     
     
         21 . The method of  claim 15 , wherein the post-oxidation annealing includes maintaining the wafer at a temperature between about 950° C. and about 1200° C. for a time period between about 1 second and about 20 seconds. 
     
     
         22 . The method of  claim 11 , wherein removing the screening oxide layer from the plurality of fins includes a cleaning using Hydrogen fluoride (HF) vapor. 
     
     
         23 . The method of  claim 11 , wherein removing the screening oxide layer from the plurality of fins includes a wet etching process. 
     
     
         24 . The method of  claim 23 , wherein the wet etching process is performed using an etching agent including HF acid. 
     
     
         25 . The method of  claim 11 , wherein the gate stack includes at least one of a poly silicon gate, a fully silicided gate and a metal gate. 
     
     
         26 . The method of  claim 10 , wherein the dopant comprises at least one of the group of materials consisting of Boron difluoride and Boron trifluoride and implanted into the plurality of fins in an NMOS device using an implant dose between about 5E13 atoms/cm 2  and about 6E15 atoms/cm 2 . 
     
     
         27 . The method of  claim 10 , wherein the dopant comprises at least one of the group of materials consisting of Boron difluoride and Boron trifluoride and implanted into the plurality of fins, the plurality of fins includes n-type doping material. 
     
     
         28 . The method of  claim 10 , wherein the dopant comprises at least one of the group of materials consisting of Boron difluoride and Boron trifluoride and implanting the plurality of fins includes implanting a plurality of n-doped fins in a PMOS device. 
     
     
         29 . The method of  claim 26 , wherein implanting the dopant on the plurality of fins is performed at an implantation angle that is determined by solving the equation:
   tan( a )= s/h      
       where, “s” is the spacing between two consequent fins, and “h” is the height of the silicon fins. 
     
     
         30 . A method for fabricating a semiconductor wafer, the method comprising:
 providing a substrate having a buried silicon oxide layer and a single crystal silicon layer disposed above the substrate;   implanting a dopant into the buried silicon oxide layer;   providing a gate insulator disposed on the silicon layer after implanting the dopant into the buried silicon oxide layer;   annealing the semiconductor wafer; and   providing a gate stack.   
     
     
         31 . The method of  claim 30 , wherein the dopant includes at least one of the group of materials consisting of Fluorine, Boron difluoride, Boron trifluoride, Chlorine, Hydrogen, Deuterium, Nitrogen, Argon, Xenon, Neon, and Krypton. 
     
     
         32 . The method of  claim 30 , wherein the gate insulator comprises depositing a high-k dielectric material onto the single crystal silicon layer.