Reduced-resistance finfets by sidewall silicidation and methods of manufacturing the same

Abstract

In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

1 . A method of manufacturing a finFET, comprising: 
 providing a substrate; and    forming at least one source/drain diffusion region of the finFET on the substrate;    wherein each source/drain diffusion region includes: 
 an interior region of unsilicided silicon; and  
 silicide formed on a top surface and sidewalls of the region of unsilicided silicon.  
   
   
   
       2 . The method of  claim 1  wherein forming at least one source/drain diffusion region of the finFET on the substrate includes increasing a surface area of a silicon-silicide interface in the source/drain diffusion region.  
   
   
       3 . The method of  claim 1  further comprising forming a gate having a predetermined work function on the substrate.  
   
   
       4 . A finFET, comprising: 
 at least one source/drain diffusion region formed on a substrate;    wherein each source/drain diffusion region includes: 
 an interior region of unsilicided silicon; and  
 silicide formed on a top surface and sidewalls of the region of unsilicided silicon.  
   
   
   
       5 . The finFET of  claim 4  wherein each source/drain diffusion region further includes a silicon-silicide interface having an increased surface area.  
   
   
       6 . The finFET of  claim 4  wherein a distance between the silicide formed on the top surface and sidewalls of the region of unsilicided silicon and a gate region of the finFET is based on a spacer width.  
   
   
       7 . The finFET of  claim 6  wherein the spacer is about 10 nm to about 100 nm wide.  
   
   
       8 . The finFET of  claim 4  further comprising a gate; 
 wherein a work function of the gate is substantially equal to the work function of the source-drain diffusions.    
   
   
       9 . The finFET of  claim 4  wherein the silicide has a resistivity of about 10 micro-ohm-cm to about 100 micro-ohm-cm.  
   
   
       10 . A substrate, comprising: 
 a finFET having: 
 at least one source/drain diffusion region formed on the substrate;  
 wherein each source/drain diffusion region includes: 
 an interior region of unsilicided silicon; and  
 silicide formed on a top surface and sidewalls of the region of unsilicided silicon.  
 
   
   
   
       11 . The substrate of  claim 10  wherein the each source/drain diffusion region further includes a silicon-silicide interface having an increased surface area.  
   
   
       12 . The substrate of  claim 10  wherein a distance between the silicide formed on the top surface and sidewalls of the region of unsilicided silicon and a gate region of the finFET is based on a spacer width.  
   
   
       13 . The substrate of  claim 12  wherein the spacer is about 10 nm to about 100 nm wide.  
   
   
       14 . The substrate of  claim 10  further comprising a gate; 
 wherein a work function of the gate is substantially equal to the work function of the source-drain diffusions.    
   
   
       15 . The substrate of  claim 10  wherein the silicide has a resistivity of about 10 micro-ohm-cm to about 100 micro-ohm-cm.