Thin film transistor array substrate and manufacturing method thereof

Abstract

A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are disposed on the substrate and define a plurality of pixel regions. A plurality of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A plurality of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

1 . A thin film transistor array substrate comprising:
 a substrate;   a plurality of scan lines and a plurality of source lines disposed on the substrate, and define a plurality of pixel regions on the substrate;   a plurality of storage capacitance lines disposed on the substrate in a direction extending along the scan lines and across the pixel regions, each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion; and   a plurality of patterned thin films disposed on the storage capacitance lines and above the cross portion.   
   
   
       2 . The thin film transistor array substrate according to  claim 1 , further comprising an insulating layer disposed on the scan lines and the storage capacitance lines. 
   
   
       3 . The thin film transistor array substrate according to  claim 2 , wherein the patterned thin films are disposed on the insulating layer. 
   
   
       4 . The thin film transistor array substrate according to  claim 1 , wherein the patterned thin films are further disposed on the scan lines and above a cross portion of the scan lines and the source lines. 
   
   
       5 . The thin film transistor array substrate according to  claim 1 , wherein each of the pixel regions comprises a pixel electrode. 
   
   
       6 . The thin film transistor array substrate according to  claim 5 , wherein each of the pixel regions further comprises a transistor electrically connected with the pixel electrode. 
   
   
       7 . A manufacturing method of a thin film transistor array substrate, comprising:
 forming a first patterned metal layer on a substrate to define a plurality of scan lines and a plurality of storage capacitance lines, the storage capacitance lines disposed in a direction extending along the scan lines;   forming an insulating layer on the first patterned metal layer;   forming a second patterned metal layer to define a plurality of source lines, the source lines and the scan line define a plurality of pixel regions, and each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion; and   forming a patterned layer on the insulating layer to define a plurality of patterned thin films disposed on the storage capacitance lines and above the cross portion.   
   
   
       8 . The manufacturing method of a thin film transistor array substrate according to  claim 7 , further comprising the step of forming a plurality of pixel electrodes in the pixel regions. 
   
   
       9 . The manufacturing method of a thin film transistor array substrate according to  claim 8 , further comprising the step of forming a plurality of transistors in the pixel regions to electrically connect with the pixel electrodes. 
   
   
       10 . The manufacturing method of a thin film transistor array substrate according to  claim 9 , further comprising the step of forming each source electrode and each drain electrode of the transistors at the second patterned metal layer. 
   
   
       11 . The manufacturing method of a thin film transistor array substrate according to  claim 9 , further comprising the step of forming an ohmic contact thin film for each of the transistors at the patterned layer. 
   
   
       12 . The manufacturing method of a thin film transistor array substrate according to  claim 7 , further comprising the step of forming the patterned thin films on the scan lines at a cross portion of the scan lines and the source lines to cover the cross portion.