Semiconductor data processing device and data processing system

Abstract

Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

1 - 31 . (canceled)  
   
   
       32 . A semiconductor data processor, comprising: 
 a first internal circuit;    a second internal circuit;    a power circuit generating internal voltage including a high level potential and a low level potential;    a first internal power line providing said internal voltage of high level potential and coupled to said power circuit;    a second internal power line providing said internal voltage of low level potential and coupled to said power circuit;    a first power switch coupled to between said first internal circuit and said first internal power line, and    a second power switch coupled to between said first internal circuit and said second internal power line,    wherein said first internal circuit includes a central processing unit and a non-volatile memory unit accessed by said central processing unit,    wherein said second internal circuit includes a detection circuit detecting an external bus state, and    wherein said power circuit controls said first and second power switches, and halts providing said internal voltage to said first internal circuit after detecting an inactive state of said external bus.    
   
   
       33 . A semiconductor data processor according to  claim 32 , 
 wherein said detection circuit is included in a USB interface circuit, and    wherein said detection circuit is provided said internal voltage, after detection of said inactive state of said external bus.    
   
   
       34 . A semiconductor data processor according to  claim 33 , 
 wherein when said detection circuit detects an active state of said external bus, said power circuit controls said first and second power switches turning off, and provides said internal voltage to said first internal circuit and second internal circuit.    
   
   
       35 . A semiconductor data processor according to  claim 33 , further comprising a system controller, 
 wherein said system controller includes a circuit which is included in said second circuit,    wherein said circuit is provided said internal voltage after detection of said inactive state of said external bus by said detection circuit, and    wherein said circuit controls said power circuit for providing said internal voltage to said first internal circuit based on a detected state of said external bus.    
   
   
       36 . A semiconductor data processor according to  claim 33 , 
 wherein said power circuit turns off said first and second power switches to provide said internal voltage to said first internal circuit, after detection of an active state of said external bus by said detection circuit.    
   
   
       37 . A semiconductor data processor according to  claim 36 , further comprising a system controller, 
 wherein said system controller is operable to control operation modes of said data processor,    wherein said operation modes include an active state and a standby state, and    wherein said operation mode changes said active state to said standby state after said external bus takes said inactive state.    
   
   
       38 . A semiconductor data processor according to  claim 37 , 
 wherein said system controller controls to stop providing clock signals to said first and second internal circuits in said standby state.