Fabricating method of silicon layer with high resistance

Abstract

A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers and the interface layer have dopants therein. The amount of implanted dopants is about 1*10 14 ˜5*10 15 ions/cm 2 , and the silicon material layers have different grain boundaries.

1 . A method of fabricating a silicon layer with a high resistance, comprising: 
 forming a silicon layer on a substrate, the step of forming the silicon layer comprising: 
 (a) forming a silicon material layer on the substrate;  
 (b) forming an interface layer on the silicon material layer, wherein a material of the interface layer is different from that of the silicon material layer; and  
 (c) forming another silicon material layer on the interface layer; and  
   implanting dopants in the silicon layer, wherein an amount of the implanted dopants is about 1*10 14 ˜5*10 15  ions/cm 2 .    
   
   
       2 . The method according to  claim 1 , wherein the method of fabricating the interface layer comprises using ammonia, using a gas containing oxygen, or removing the substrate from a chamber and placing the substrate in the chamber again.  
   
   
       3 . The method according to  claim 1 , wherein a thickness of the interface layer is about 0˜30 Å.  
   
   
       4 . The method according to  claim 1 , wherein a thickness of the interface layer is about 0˜20 Å.  
   
   
       5 . The method according to  claim 1 , wherein a thickness of the interface layer is about 0˜10 Å.  
   
   
       6 . The method according to  claim 1 , wherein the dopants comprises boron (B), boron difluoride (BF 2 ), phosphorous (P) or arsenic (As).  
   
   
       7 . The method according to  claim 1 , further comprising repeating the steps (b) and (c) for at least one time after the step (c) and before the step of implanting the dopants in the silicon layer.  
   
   
       8 . The method according to  claim 7 , wherein the repeated step (c) is performed with a different method from that of the step (c).  
   
   
       9 . The method according to  claim 1 , wherein the substrate is formed with a dielectric layer thereon, and a portion of the silicon material layer is at least disposed on the dielectric layer.  
   
   
       10 . The method according to  claim 9 , wherein the dielectric layer comprises a gate dielectric layer, a shallow trench isolation (STI) or a field oxide isolation.  
   
   
       11 . The method according to  claim 1 , further comprising performing a thermal process for the silicon layer after the step of implanting the dopants in the silicon layer.  
   
   
       12 . The method according to  claim 1 , wherein a thickness of the silicon layer is smaller than 5000 Å.  
   
   
       13 . The method according to  claim 1 , wherein a lowest silicon material layer is at least 200 Å thick.