Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage

Abstract

The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

1 . A method of fabricating a semiconductor structure comprising: 
 providing a structure that at includes at least one gate region located on a surface of a semiconductor substrate, said at least one gate region comprising source/drain regions and source/drain extension regions in said semiconductor substrate that are separated by a channel region, a gate dielectric and a gate conductor located above said channel region, an offset spacer located on sidewalls of at least said gate conductor and an outer spacer adjacent said offset spacer and silicide contacts located atop the source/drain regions adjacent said outer spacer;    removing said outer spacer to expose a surface portion of the semiconductor substrate including said source/drain extension regions; and    selectively plating a metallic or intermetallic material on said exposed surface portion of said semiconductor substrate including said source/drain extension regions.    
   
   
       2 . The method of  claim 1  wherein said providing said structure comprises deposition, lithography and etching or a replacement gate process.  
   
   
       3 . The method of  claim 1  wherein said removing of said outer spacer is performed by a selective isotropic etching process.  
   
   
       4 . The method of  claim 3  wherein said selective isotropic etching comprises HF as a chemical etchant.  
   
   
       5 . The method of  claim 3  wherein said selective isotropic etching comprises reactive-ion etching using a gas containing F, O, C and N.  
   
   
       6 . The method of  claim 1  wherein said selectively plating is by electroless plating.  
   
   
       7 . The method of  claim 1  wherein said selectively plating is by electro plating.  
   
   
       8 . The method of  claim 1  wherein said metal or intermetallic material extends on and covers exposed surfaces of said silicide contacts.  
   
   
       9 . The method of  claim 1  wherein said metallic or intermetallic material comprises W, Al, Cu, Au, Pt, Pd, Ni, Co, Re, Rh, Ag, TiN, Ti, TaN, WN or alloys thereof.  
   
   
       10 . The method of  claim 1  wherein said metallic or intermetallic material comprises CoWP.  
   
   
       11 . The method of  claim 1  further comprising forming a liner that introduces stress into said channel region, said liner is located over said semiconductor substrate including said silicide contacts, said metallic or intermetallic material, said gate dielectric and said gate conductor.