Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same

Abstract

A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.

1 . A semiconductor device comprising: 
 a first interlayer insulating layer formed on a semiconductor substrate, wherein the first interlayer insulating layer comprises interleaved etched residual portions and non-etched portions, wherein each etched residual portion defines the geometry of a contact hole and a corresponding line-shaped trench connected to the contact hole in a contact region, and wherein each etched residual portion comprises a rounded shoulder portion defining the geometry of the contact region;    a contact plug filling the contact hole and a corresponding wiring layer filling the line-shaped trench, wherein the contact plug electrically connects a conductive region of the semiconductor substrate with the wiring layer through the contact region.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the width of the contact plug broadens in a first direction as it extends from a lower section proximate the semiconductor substrate through a middle section and into an upper section proximate the contact region.  
     
     
         3 . The semiconductor device of  claim 1 , further comprising: 
 a first etch stop insulating layer formed between the semiconductor substrate and the first interlayer insulating film.    
     
     
         4 . The semiconductor device of  claim 1 , further comprising: 
 residual portions of a buffer insulating layer formed on at least some of the interleaved non-etched portions of the first interlayer insulating film.    
     
     
         5 . The semiconductor device of  claim 4 , wherein the residual portions of the buffer insulating layer are formed on alternating ones of the non-etched portions of the first interlayer insulating layer.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the interleaved etched residual portions of the first interlayer insulating layer define a corresponding plurality of contact plugs connected to respective conductive regions of the semiconductor substrate with a corresponding wiring layer from a plurality of wiring layers separated with a constant pitch.  
     
     
         7 . The semiconductor device of  claim 6 , wherein the plurality of contact plugs forms a plurality of linearly arranged direct contacts separated by the constant pitch and the plurality of wiring layers comprises a plurality of bit lines corresponding one for one with the plurality of linearly arranged direct contacts.  
     
     
         8 . The semiconductor device of  claim 6 , wherein the plurality of contact plugs and the plurality of wiring lines are formed from the same conductive material.  
     
     
         9 . A method of manufacturing a semiconductor device, comprising: 
 forming a first etch-stop insulating layer on a semiconductor substrate;    forming an interlayer insulating layer on the first etch-stop insulating layer;    forming a composite hardmask pattern in a first direction on the interlayer insulating film, wherein the composite hardmask pattern comprises residual portions of a buffer insulating film;    forming a crossing mask pattern in a second direction different from the first direction on the composite hardmask pattern, wherein the crossing mask pattern comprises an opening selectively exposing portions of the residual portions of the buffer insulating film;    using the combination of the composite hardmask pattern and the crossing mask pattern, etching the exposed portions of the residual portions of the buffer insulating layer to form contact holes to a depth leaving a residual separation thickness between bottom surfaces of the contact holes and the first etch-stop insulating layer;    removing the crossing mask pattern to expose residual etched portions of the interlayer insulating film;    etching the exposed residual etched portions of the interlayer insulating layer to form a plurality of line-shaped trenches and simultaneously removing the residual separation thickness to form a plurality of contact holes selectively exposing portions of the first etch-stop insulating layer;    filling the plurality of contact holes and the plurality of line-shaped trenches with at least one conductive material to simultaneously and integrally form a plurality of contact plugs in the plurality of contact holes, and a respectively connected plurality of wiring layers in the plurality of line-shaped trenches.    
     
     
         10 . The method of  claim 9 , wherein forming the composite hardmask pattern on the interlayer insulating layer comprises: 
 forming a plurality of parallel first mask patterns on the interlayer insulating layer extending in the first direction and separated by a first pitch;    forming a buffer insulating layer to cover upper and sidewall portions of the plurality of first mask patterns and to form a plurality of parallel recessed regions;    forming an interleaving plurality of second mask patterns in the plurality of recessed regions and patterning the buffer insulating layer to form the residual portions of the buffer insulating film,    wherein the plurality of first mask patterns, the plurality of second mask patterns, and the residual portions of the buffer insulating layer are formed in a self-aligned manner, and the plurality of first mask patterns and the plurality of second mask patterns are separated by a final pitch less than the first pitch.    
     
     
         11 . The method of  claim 10 , wherein the buffer insulating layer has different etch characteristics in relation to a defined etch process than the material forming the plurality of first mask patterns and the plurality of second mask patterns.  
     
     
         12 . The method of  claim 9 , wherein following etching of the exposed residual portions of the interlayer insulating film, each one of the etched residual portions of the interlayer insulating layer comprises a rounded shoulder portion defining a contact region.  
     
     
         13 . The method of  claim 12 , wherein respective contact plugs and wiring layers are electrically connected through the contact region, such that the width of the contact plug in the first direction broadens as the contact plug extends from a lower section through a middle section to an upper section.  
     
     
         14 . The method of  claim 9 , wherein the residual separation thickness is substantially equal to a desired thickness for the plurality of wiring layers.  
     
     
         15 . The method of  claim 9 , wherein the first and second directions are orthogonal.  
     
     
         16 . A method of manufacturing a semiconductor device, comprising: 
 forming a first etch-stop insulating layer on a semiconductor substrate;    forming a first interlayer insulating layer on the first etch-stop insulating layer;    forming a second etch-stop insulating layer on the first interlayer insulating film;    forming a second interlayer insulating layer on the second etch-stop insulating film;    forming a composite hardmask pattern in a first direction on the second interlayer insulating film, wherein the composite hardmask pattern comprises residual portions of a buffer insulating film;    forming a crossing mask pattern in a second direction different from the first direction on the composite hardmask pattern, wherein the crossing mask pattern comprises an opening selectively exposing portions of the residual portions of the buffer insulating film;    using the combination of the composite hardmask pattern and the crossing mask pattern, etching the exposed portions of the residual portions of the buffer insulating layer to form contact holes though the second interlayer insulating layer and second etch-stop insulating layer to a depth leaving a residual separation thickness between bottom surfaces of the contact holes and the first etch-stop insulating layer;    removing the crossing mask pattern to expose residual etched portions of the second interlayer insulating film;    etching the exposed residual etched portions of the second interlayer insulating layer down to the second etch-stop insulating layer to form a plurality of line-shaped trenches and to simultaneously remove the residual separation thickness to form a plurality of contact holes selectively exposing portions of the first etch-stop insulating layer;    filling the plurality of contact holes and the plurality of line-shaped trenches with at least one conductive material to simultaneously and integrally form a plurality of contact plugs in the plurality of contact holes, and a respectively connected plurality of wiring layers in the plurality of line-shaped trenches.    
     
     
         17 . The method of  claim 16 , wherein forming the composite hardmask pattern on the interlayer insulating layer comprises: 
 forming a plurality of parallel first mask patterns on the first interlayer insulating layer extending in the first direction and separated by a first pitch;    forming a buffer insulating layer to cover upper and sidewall portions of the plurality of first mask patterns and to form a plurality of parallel recessed regions;    forming an interleaving plurality of second mask patterns in the plurality of recessed regions and patterning the buffer insulating layer to form the residual portions of the buffer insulating film,    wherein the plurality of first mask patterns, the plurality of second mask patterns, and the residual portions of the buffer insulating layer are formed in a self-aligned manner, and the plurality of first mask patterns and the plurality of second mask patterns are separated by a final pitch less than the first pitch.    
     
     
         18 . The method of  claim 17 , wherein the buffer insulating layer has different etch characteristics in relation to a defined etch process than the material forming the plurality of first mask patterns and the plurality of second mask patterns.  
     
     
         19 . The method of  claim 16 , wherein the residual separation thickness is substantially equal to a desired thickness for the plurality of wiring layers.  
     
     
         20 . The method of  claim 16 , wherein the first and second directions are orthogonal.