Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same

Abstract

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

1 . A semiconductor device comprising:
 a semiconductor substrate having a cell region and a peripheral circuit region defined therein;   a buried word line in the substrate in the cell region and having a top surface lower than top surfaces of cell active regions in the cell region;   a gate line on the substrate in the peripheral circuit region; and   a unitary word line interconnect in the substrate in the peripheral circuit region, the word line interconnect comprising a first portion contacting the buried word line and having a top surface lower than top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the second portion of the word line interconnect extends vertically from the first portion of the word line interconnect to contact a bottom surface of the gate line. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the top surface of the first portion of the word line interconnect is at substantially the same level as the top surface of the buried word line. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the first portion of the word line interconnect has substantially the same cross-sectional area as the buried word line. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the word line interconnect and the buried word line comprise a common metal layer. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the gate line has a top surface that is higher than top surfaces of peripheral circuit active regions in the peripheral circuit region. 
   
   
       7 . The semiconductor device of  claim 1 , further comprising an insulating pattern disposed on the first portion of the word line interconnect and the buried word line. 
   
   
       8 . The semiconductor device of  claim 7 , wherein a bottom surface of the insulating pattern is lower than the top surfaces of the cell active regions. 
   
   
       9 . The semiconductor device of  claim 7 , further comprising a bit line disposed on the insulating pattern and crossing the buried word line. 
   
   
       10 . The semiconductor device of  claim 9 , further comprising:
 first and second spaced-apart gate lines on the substrate in the peripheral circuit region on respective sides of the bit line;   a buried peripheral circuit interconnect in the substrate in the peripheral circuit region beneath the bit line, the buried peripheral circuit interconnect connecting the first and second gate lines and having a portion beneath the bit line that has a top surface at substantially the same level as the top surface of the buried word line.   
   
   
       11 . The semiconductor device of  claim 1 , wherein the first portion of the word line interconnect is laterally offset with respect to the buried word line. 
   
   
       12 . A method of fabricating a semiconductor device, comprising:
 forming an isolation region in a semiconductor substrate, the isolation region defining cell active regions in a cell region and peripheral circuit active regions in a peripheral circuit region;   forming a word line trench in the substrate in the cell region and an adjoining word line interconnect trench in the peripheral circuit region;   forming a word line pattern in the word line trench and a word line interconnect pattern in the word line interconnect trench;   forming a gate line on the substrate in the peripheral circuit region, the gate line having an end portion that overlaps the word line interconnect pattern;   etching back the word line pattern and the word line interconnect pattern to form word line in the word line trench having a top surface lower than top surfaces of the cell active regions and a word line interconnect in the word line interconnecting trench having a first portion connected to the word line and a top surface lower than the top surfaces of the cell active regions and a second portion extending vertically from the first portion to contact a bottom surface of the gate line; and   forming an insulating pattern on the buried word line and the first portion of the word line interconnect.   
   
   
       13 . The method of  claim 12 , wherein forming a word line trench in the cell region and an adjoining word line interconnect trench in the peripheral circuit region comprises:
 forming a first sacrificial mask pattern on the substrate having the isolation layer;   forming sacrificial spacers on sidewalls of the first sacrificial mask pattern;   forming a second sacrificial mask pattern filling a gap between the sacrificial spacers;   removing the sacrificial spacers; and   etching the isolation layer and the semiconductor substrate using the first and second sacrificial mask patterns as etching masks to form the word line trench and the word line interconnect trench.   
   
   
       14 . The method of  claim 13 , wherein forming a first sacrificial mask pattern on the substrate having the isolation layer is preceded by:
 forming a peripheral circuit gate dielectric layer on the peripheral circuit active regions;   forming a peripheral circuit gate conductive layer on the peripheral circuit gate dielectric layer; and   forming a sacrificial oxide layer on the peripheral circuit gate conductive layer.   
   
   
       15 . The method of  claim 14 , wherein forming a gate line comprises:
 etching the first and second sacrificial mask patterns and the sacrificial oxide layer to expose the peripheral circuit gate conductive layer;   forming a metal layer covering the peripheral circuit gate conductive layer, the word line pattern, and the word line interconnect pattern; and   patterning the metal layer and the peripheral circuit gate conductive layer to form the gate line.   
   
   
       16 . The method of  claim 12 , wherein the word line pattern and the word line interconnect pattern are formed from a common metal layer. 
   
   
       17 . The method of  claim 12 , wherein a bottom surface of the insulating pattern is lower than top surfaces of the cell active regions. 
   
   
       18 . The method of  claim 12 , further comprising forming a bit line on the insulating pattern and crossing the buried word line. 
   
   
       19 . The method of  claim 18 , further comprising:
 forming a peripheral circuit interconnect trench in the substrate in the peripheral circuit region concurrent with forming the word line trench in the substrate in the cell region and the adjoining word line interconnect trench in the peripheral circuit region;   forming a peripheral circuit interconnect pattern in the peripheral circuit interconnect trench concurrent with forming the word line pattern in the word line trench and the word line interconnect pattern in the word line interconnect trench;   forming second and third spaced apart gate lines in the peripheral circuit region on respective sides of the bit line concurrent with forming the first gate line on the substrate in the peripheral circuit region, the first and second gate lines overlapping and contacting the peripheral circuit interconnect pattern;   etching back the peripheral circuit interconnect pattern concurrent with etching back the word line pattern and the word line interconnect pattern to form a peripheral circuit interconnect having a first portion with a top surface that is lower than a top surface of the peripheral circuit active regions and second portions that extend vertically from the first portion to contact bottom surfaces of respective ones of the second and third gate lines; and   forming an insulating pattern on the first portion of the peripheral circuit interconnect concurrent with forming the insulating pattern on the buried word line and the first portion of the word line interconnect.   
   
   
       20 . The method of  claim 12 , wherein the buried word line extends along a line across the cell region, and wherein the first portion of the word line interconnect is laterally offset with respect to the line. 
   
   
       21 .- 44 . (canceled)