Flip chip semiconductor assembly with variable volume solder bumps

Abstract

A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

1 . A method of manufacturing a semiconductor chip assembly comprising a die with an integrated circuit formed thereon comprising a plurality of die-pads, and a substrate comprising a plurality of substrate-pads said method comprising:
 (i) forming conductive column bumps extending from said die-pads, at least two of said column bumps having different volumes;   (ii) attaching each of said column bumps directly to a corresponding one of said substrate-pads to form a subassembly; and   (iii) reflowing said column bumps to form solder bumps of varying volume to form electrical and mechanical connections between said die-pads and said substrate-pads.   
     
     
         2 . The method of  claim 1  further comprising, forming under-bump metallization (UBM) on said die-pads before said forming conductive column bumps. 
     
     
         3 . The method of  claim 1 , further comprising dispensing an underfill between said die and said substrate. 
     
     
         4 . The method of  claim 3 , further comprising curing said underfill. 
     
     
         5 . The method of  claim 1  wherein said column bumps are solder bumps. 
     
     
         6 . The method of  claim 5 , wherein said solder bumps are substantially lead free. 
     
     
         7 . The method of  claim 6 , wherein said solder bumps comprise 63% Sn and 37% Pb eutectic, or 96.5% Sn, 3% Ag and 0.5% Cu. 
     
     
         8 . The method of  claim 1 , wherein said column bumps comprise wire stud bumps. 
     
     
         9 . The method of  claim 1 , wherein said column bumps are plated bumps. 
     
     
         10 . A method of manufacturing a semiconductor chip assembly comprising:
 forming a plurality of metallized die-pads extending from a semiconductor die;   forming, from a conductive reflowable material, column bumps extending from said metallized, die-pads at least two of said column bumps having different volumes;   aligning said column bumps with substrate-pads of a substrate, to place said column bumps in contact with said die-pads, prior to reflowing said column bumps;   reflowing said column bumps on said die-pads to form electrical and mechanical connections between said die-pads and said substrate-pads.   
     
     
         11 . The method of  claim 10 , further comprising dispensing an underfill between said die and said substrate. 
     
     
         12 . The method of  claim 10 , wherein said solder bumps are substantially lead free. 
     
     
         13 . A semiconductor chip assembly, comprising:
 a die having an integrated circuit formed thereon;   die pads extending from said die;   a substrate;   substrate contacts;   reflowed solder balls mechanically interconnecting said die pads to said substrate contacts, wherein at least some of said solder balls have differing volumes.   
     
     
         14 . The semiconductor chip assembly of  claim 13  wherein the ratio of the volumes of largest of said solder balls to the smallest is about 2:1. 
     
     
         15 . The semiconductor chip assembly of  claim 13 , wherein solder balls proximate at least one corner of said die have a volume at least 1.1 times the volume of solder balls proximate the center. 
     
     
         16 . The semiconductor chip assembly of  claim 13 , further comprising a cured underfill between said die and said substrate. 
     
     
         17 . The semiconductor chip assembly of  claim 13 , wherein said solder bumps are substantially lead free. 
     
     
         18 . A semiconductor chip subassembly, comprising a die having an integrated circuit formed thereon; and die pads formed on said die wherein at least some of said die pads have differing surface areas. 
     
     
         19 . A semiconductor chip subassembly, comprising a die having an integrated circuit formed thereon, die pads formed on said die and column bumps extending from said die pads, wherein at least some of said column bumps have differing volumes. 
     
     
         20 . A semiconductor chip assembly comprising the semiconductor chip subassembly of  claim 19 . 
     
     
         21 . The semiconductor chip subassembly of  claim 19 , wherein at least one of said column bumps that is larger than at least one other one of said column bumps is placed in thermal communication with an area of greater heat dissipation in said die. 
     
     
         22 . The semiconductor chip assembly of  claim 13 , wherein at least one of said solder balls that is larger than at least one other one of said solder balls is placed in thermal communication with an area of greater heat dissipation in said die. 
     
     
         23 . The semiconductor chip assembly of  claim 22 , wherein at least one of said solder balls that is larger than at least one other one of said solder balls is proximate an edge of said semiconductor chip assembly, to provide increased mechanical bonding to said edge when said semiconductor chip assembly is attached to a board. 
     
     
         24 . The semiconductor chip assembly of  claim 22 , wherein said at least one of said solder balls that is larger than at least one other one of said solder balls, is an area of increased mechanical stress in said semiconductor chip assembly. 
     
     
         25 . The semiconductor chip assembly of  claim 22 , wherein said at least one of said solder balls that is larger than at least one other one of said solder balls, conducts more current than at least one other one of said solder balls.