Semiconductor package and method for manufacturing the same

Abstract

A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

1 . A semiconductor package comprising: 
 a chip having an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of bonding pads disposed on the active surface and electrically connected to the optical component;    a plurality of via holes formed through the chip and electrically connected to the plurality of bonding pads;    a lid attached on the active surface of the chip; and    a plurality of metal traces being disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defining a plurality of solder pads thereon.    
   
   
       2 . The semiconductor package as claimed in  claim 1 , further comprising an adhesive ring disposed around the optical component for attaching the lid on the active surface of the chip.  
   
   
       3 . The semiconductor package as claimed in  claim 2 , wherein the adhesive ring is made of an adhesive material having a plurality of spacers mixed thereinto.  
   
   
       4 . The semiconductor package as claimed in  claim 1 , having at least one side surface wherein the plurality of via holes are exposed out of the side surface.  
   
   
       5 . The semiconductor package as claimed in  claim 1 , further comprising a plurality of pad extension traces for electrically connecting the via holes with the bonding pads.  
   
   
       6 . The semiconductor package as claimed in  claim 1 , further comprising a plurality of compliant pads formed between the back surface of the chip and the metal traces and corresponding to the solder pads.  
   
   
       7 . The semiconductor package as claimed in  claim 1 , further comprising a solder mask, which covers the back surface of the chip and the metal traces with the solder pads exposed therefrom.  
   
   
       8 . The semiconductor package as claimed in  claim 7 , wherein the solder mask further covers at least one side surface of the chip.  
   
   
       9 . The semiconductor package as claimed in  claim 1 , further comprising a plurality of solder balls respectively disposed on the solder pads.  
   
   
       10 . The semiconductor package as claimed in  claim 1 , wherein the lid is made of transparent material.  
   
   
       11 . The semiconductor package as claimed in  claim 10 , wherein the transparent material is selected form a group consisting of glass, acrylic resin and sapphire.  
   
   
       12 . The semiconductor package as claimed in  claim 1 , wherein the optical component is formed by complementary metal oxide semiconductor (CMOS).  
   
   
       13 . The semiconductor package as claimed in  claim 6 , wherein the compliant pads are made of photosensitive benzocyclobutene polymer.  
   
   
       14 . The semiconductor package as claimed in  claim 7 , the solder mask is made of photosensitive benzocyclobutene polymer.