Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof

Abstract

A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

1 . A method for fabricating a capacitor structure comprising; 
 forming at least one aperture within a dielectric layer located over a substrate, so that a pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture;    forming a pair of capacitor plates upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, the pair of capacitor plates not filling the aperture; and    forming a capacitor dielectric layer located interposed between the pair of capacitor plates and filling the aperture.    
   
   
       2 . The method of  claim 1  wherein the forming the aperture uses at least in part the pair of conductor interconnection layers as a mask.  
   
   
       3 . The method of  claim 1  wherein the forming the pair of capacitor plates comprises forming a capacitor plate material layer into the aperture and ansiotropically etching the capacitor plate material layer to form an ansiotropically etched capacitor plate material layer covering a periphery of the aperture.  
   
   
       4 . The method of  claim 3  further comprising further etching the anisotropically etched capacitor plate material layer to form the pair of capacitor plates.  
   
   
       5 . The method of  claim 4  wherein the further etching uses a mask.  
   
   
       6 . A method for fabricating a capacitor structure comprising; 
 forming at least one aperture within a dielectric layer located over a substrate, the aperture having a first pair of opposite sidewalls that is at least substantially vertical and a second pair of opposite sidewalls that is at least substantially sloped and that also separates the first pair of opposite sidewalls, and further where a pair of conductor interconnection layers embedded within the dielectric layer terminates at the first pair of opposite sidewalls;    forming a pair of capacitor plates located upon the first pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, the pair of capacitor plates not filling the aperture; and    forming a capacitor dielectric layer located interposed between the pair of capacitor plates and filling the aperture.    
   
   
       7 . The method of  claim 6  wherein the forming the aperture uses a tapered patterned photoresist layer.  
   
   
       8 . The method of  claim 7  wherein the tapered patterned photoresist layer recedes when forming the aperture.  
   
   
       9 . The method of  claim 6  wherein the forming the aperture uses at least in part the pair of conductor interconnection layers as a mask.  
   
   
       10 . The method of  claim 6  wherein the forming the pair of capacitor plates uses a single anisotropic plasma etch step.