ID installable LSI, secret key installation method, LSI test method, and LSI development method

Abstract

In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

1 . An ID installable LSI comprising: 
 a decoding section for receiving an ID signal representing the ID from outside the LSI, decoding the ID signal, and outputting the decoded signal;    a value holding circuit for receiving the decoded signal, writing the value represented by the decoded signal therein when an operation setting signal is active, and holding the written value when the operation setting signal is inactive; and    an ID memory part for storing the value held in the value holding circuit as the ID.    
   
   
       2 . The ID installable LSI of  claim 1 , wherein the value holding circuit is a fuse circuit having a nonvolatile element and the like.  
   
   
       3 . The ID installable LSI of  claim 1 , further comprising a random number generation circuit for receiving the value held in the value holding circuit and generating a random number based on the received value, 
 wherein the ID memory part stores the random number generated by the random number generation circuit in place of the value held in the value holding circuit.    
   
   
       4 - 6 . (canceled)  
   
   
       7 . A method for installing a secret key in an LSI, comprising: 
 a first step of determining the position to be bumped in a pad portion of a second LSI according to an ID provided for a first LSI;    a second step of bumping the position in the second LSI determined in the first step; and    a third step of bonding the bumped second LSI to the first LSI.    
   
   
       8 . (canceled)  
   
   
       9 . An LSI test method comprising the step of: 
 testing an LSI with a tester LSI, the LSI having a memory part from which an ID value is output according to an address supplied,    wherein the LSI comprises a first test circuit,    the tester LSI comprises a second test circuit, the first and second test circuits, in the state of being connected with each other, outputting the same value as that output from the memory part when receiving the same address as that supplied to the memory part, and    the step of testing comprises connecting the second test circuit of the tester LSI to the first test circuit of the LSI and comparing the output of the connected first and second test circuits with the output of the memory part.    
   
   
       10 . (canceled)