Data processor

Abstract

The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

1 - 15 . (canceled)  
   
   
       16 . A data processor comprising: 
 a central processing unit including a status register and a register set;    a plurality of register banks corresponding to said register set;    a bank number register indicating states of said register banks; and    a bank control register indicating permit using of said register banks for each of interrupt priority levels,    wherein said plurality of register banks are operable to save information of said register set,    wherein said status register includes an overflow flag indicating states of said plurality of register banks, and    wherein said overflow flag is set when an interrupt of a priority level which is permitted use of said register banks occurs in a state of said bank number register indicating that information has been saved to all of said register banks.    
   
   
       17 . A data processor according to  claim 16 , 
 wherein said central processing unit saves information of said register set to a stack area when an interrupt of priority level, which is permitted use of said register banks, occurs in state of said bank number register indicating that information has been saved to all of said register banks.    
   
   
       18 . A data processor according to  claim 17 , 
 wherein said central processing unit restores information from said stack area to said register set when said restore is instructed in a state of said overflow flag being set.    
   
   
       19 . A data processor according to  claim 18 , further comprising: 
 a program counter indicating an instruction address executed by said central processing unit,    wherein said register set is operable for saving information to said register banks, and    wherein said register set includes general purpose registers, a global register, a multiplication register, a procedure register.    
   
   
       20 . A data processor according to  claim 19 , 
 wherein information of said status register and said program counter is saved to said stack area.    
   
   
       21 . A data processor according to  claim 20 , 
 wherein said central processing unit executes a predetermined exception handling routine and saves information of said program counter to said stack area, when an interrupt occurs in a state in which information has been saved to all register banks, and said interrupt is allowed use of said register banks, and said interrupt indicates execution of said predetermined exception handling routine.    
   
   
       22 . A data processor according to  claim 16 , further comprising: 
 a memory including said plurality of register banks; and    a bus coupled to said memory and said register set,    wherein said bus has at least a number of bits of two registers included in said register set.    
   
   
       23 . A data processor according to  claim 19 , 
 wherein said central processing unit operates to effect saving of said information of said status register, said program counter and said register set in response to said occurrence of an interrupt exception.