Simultaneous Transmissions Between Multiple Master Buses and Multiple Slave Buses

Abstract

A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.

1 . An internal bus structure comprising: 
 a plurality of master buses;    a plurality of masters, wherein each master bus is directly connected to two or more of the plurality of masters;    a plurality of slave buses;    at least one slave connected to each slave bus; and    a plurality of multi-bus interfaces corresponding to the slave buses, wherein each multi-bus interface is directly connected to one respective slave bus, each multi-bus interface multiplexing the plurality of master buses to the respective slave bus.    
   
   
       2 . The internal bus structure of  claim 1 , wherein a first master on a first master bus accesses a first slave on a first slave bus through a first multi-bus interface at the same time that a second master on a second master bus accesses a second slave on a second slave bus through a second multi-bus interface.  
   
   
       3 . The internal bus structure of  claim 1 , wherein each multi-bus interface comprises: 
 a multi-bus arbiter having a plurality of inputs, each input corresponding to a respective master bus; and    a bridge connected between the multi-bus arbiter and the respective slave bus.    
   
   
       4 . The internal bus structure of  claim 3 , wherein each multi-bus interface further comprises a decoder connected to the multi-bus arbiter and the bridge, the decoder configured to decode address locations of the slaves on the slave bus.  
   
   
       5 . The internal bus structure of  claim 3 , wherein the multi-bus arbiter comprises: 
 a plurality of request buffers corresponding to the plurality of master buses, each request buffer capable of storing requests from a respective master bus;    a request selecting multiplexer having a first set of inputs configured to receive the requests directly from the plurality of master buses and a second set of inputs configured to receive the requests stored in the request buffers; and    a request phase arbiter configured to receive the requests from the plurality of master buses, provide a selection signal to the request selecting multiplexer for selecting a request from among the first set of inputs and second set of inputs, and provide a pending signal.    
   
   
       6 . The internal bus structure of  claim 1 , wherein the number of master buses is two and the number of slave buses is two.  
   
   
       7 . The internal bus structure of  claim 1 , wherein the number of master buses is greater than two and the number of slave buses is greater than two.  
   
   
       8 . The internal bus structure of  claim 1 , wherein the number of master buses is not equal to the number of slave buses.  
   
   
       9 . A bus system located within a digital device, the bus system comprising: 
 a plurality of master buses, each master bus connected to at least one master;    a first multi-bus interface connected to the plurality of master buses;    a first slave bus connected to the first multi-bus interface;    a second multi-bus interface connected to the plurality of master buses; and    a second slave bus connected to the second multi-bus interface;    a plurality of bus arbiters, each bus arbiter corresponding to a respective master bus for providing a first level of arbitration for arbitrating requests from the at least one master on the respective master bus to grant ownership of the master bus to one of the at least one requesting master;    wherein the first multi-bus interface enables a first master bus of the plurality of master buses to access the first slave bus and the second multi-bus interface enables a second master bus of the plurality of master buses to simultaneously access the second slave bus;    wherein the first multi-bus interface and the second multi-bus interface provide a second level of arbitration for granting ownership of the respective slave bus.    
   
   
       10 . The bus system of  claim 9 , wherein each multi-bus interface receives requests from the plurality of master buses, stores the requests, and selects an order of priority for processing the requests.  
   
   
       11 . The bus system of  claim 10 , wherein, when multiple simultaneous requests are made by at least two of the plurality of master buses, the multi-bus interface selects the request from the master bus with the highest priority without wait and, after processing the selected request, selects the request from the master bus with the next highest priority until all requests have been honored.  
   
   
       12 . The bus system of  claim 9 , wherein the number of master buses is not equal to the number of slave buses.  
   
   
       13 . A multi-bus interface connected to a first slave bus of a plurality of slave buses, the multi-bus interface comprising: 
 means for receiving requests from a plurality of master buses;    means for selecting a request from one of the plurality of master buses; and    means for transmitting the selected request to the first slave bus;    wherein the selecting means includes a predetermined arbitration protocol based on a first signal indicative of which of the plurality of the master buses made a request and a second signal indicative of which of the plurality of the master buses was the previous owner of the first slave bus.    
   
   
       14 . The multi-bus interface of  claim 13 , further comprising means for bridging a communication path from the plurality of master buses with the first slave bus.  
   
   
       15 . The multi-bus interface of  claim 13 , further comprising means for storing at least one request when the receiving means simultaneously receives multiple requests.  
   
   
       16 . The multi-bus interface of  claim 15 , further comprising means for transmitting a wait signal to the one or more master buses that are not highest in priority when simultaneous requests are received.  
   
   
       17 . The multi-bus interface of  claim 13 , further comprising a decoder connected to the multi-bus arbiter and the bridge, the decoder configured to decode address locations of the slaves on the slave bus.