Method of Controlling A Memory Device Having a Memory Core

Abstract

Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.

1 . A system comprising: 
 a memory controller to output a command to sample data and a strobe signal; and    a memory device to receive the command and the strobe signal, the memory device to delay sampling a first portion of the data until the strobe signal is detected,    wherein the memory device samples the first portion of the data from a signal line in response to the detection of the strobe signal.    
   
   
       2 . The system of  claim 1  wherein the memory device samples the first portion of the data synchronously with respect to a clock signal.  
   
   
       3 . The system of  claim 2  wherein the memory device samples a second portion of the data synchronously with respect to the clock signal, wherein the first portion of the data is sampled during an odd phase of the clock signal, and the second portion of the data is sampled during an even phase of the clock signal.  
   
   
       4 . The system of  claim 3  wherein the memory device samples both the first and second portions of the data during a first clock cycle of the clock signal.  
   
   
       5 . The system of  claim 1 , wherein the memory device automatically initiates a precharge operation.  
   
   
       6 . A system comprising: 
 a memory controller to output a first code, a second code, data and a strobe signal, wherein the first code specifies a write operation is to be initiated and the second code specifies a precharge operation is to be initiated automatically after initiation of the write operation; and    a memory device to receive the first and second codes synchronously with respect to a clock signal, the memory device begins sampling data upon detection of the strobe signal and the memory device writes the data to an array of memory cells during the write operation and initiates the precharge operation automatically after the write operation is initiated.    
   
   
       7 . The system of  claim 6  wherein the memory device includes a row of sense amplifiers coupled to the array to store the data during the write operation.  
   
   
       8 . The system of  claim 6  wherein the memory controller outputs an address associated with the data and the memory device receives the address synchronously with respect to the clock signal.  
   
   
       9 . The system of  claim 8  wherein the address and first and second codes are included in a packet.  
   
   
       10 . The system of  claim 8  further comprising a plurality of signal lines coupled to the memory controller and memory device, the plurality of signal lines to transport the data, address and first and second codes.  
   
   
       11 . The system of  claim 6  wherein the memory device samples a first and second portion of the data synchronously with respect to the clock signal, wherein the first portion of the data is sampled during an odd phase of the clock signal, and the second portion of the data is sampled during an even phase of the clock signal.  
   
   
       12 . The system of  claim 11  wherein the memory device samples both the first and second portions of the data during a first clock cycle of the clock signal.  
   
   
       13 . A method of operation in a memory system including a memory controller and a memory device having an array of memory cells, the method comprises: 
 outputting, from the memory controller, a command to sample data;    outputting, from the memory controller, data including first and second portions;    outputting, from the memory controller, a strobe signal;    receiving, by the memory device, the command;    detecting, by the memory device, the strobe signal; and    sampling, by the memory device, the first portion of the data by in response to detecting the strobe signal.    
   
   
       14 . The method of  claim 13  further comprising sampling the first portion of the data synchronously with respect to a clock signal provided to the memory device.  
   
   
       15 . The method of  claim 14  further comprising sampling a second portion of the data synchronously with respect to the clock signal, wherein the first portion of the data is sampled during an odd phase of the clock signal, and the second portion of the data is sampled during an even phase of the clock signal.  
   
   
       16 . The system of  claim 15  further comprising sampling both the first and second portions of the data during a first clock cycle of the clock signal.  
   
   
       17 . The system of  claim 13 , further comprising initiating automatically a precharge operation.  
   
   
       18 . A method of operation in a memory system including a memory controller and a memory device having an array of memory cells, the method comprises: 
 outputting, from the memory controller, a first code that specifies a write operation is to be initiated;    outputting, from the memory controller, a second code that specifies a precharge operation is to be initiated automatically after initiation of the write operation;    outputting, from the memory controller, data;    outputting, from the memory controller, a strobe signal;    receiving, by the memory device, the first code synchronously with respect to a clock signal;    receiving, by the memory device, the second code synchronously with respect to the clock signal;    sampling, by the memory device, the data upon detecting the strobe signal;    writing, by the memory device, the data to the array of memory cells during the write operation; and    initiating, by the memory device, the precharge operation automatically after the write operation is initiated.    
   
   
       19 . The method of  claim 18  further comprising: 
 outputting, from the memory controller, an address associated with the data; and    receiving, by the memory device, the address synchronously with respect to the clock signal.    
   
   
       20 . The system of  claim 18 , wherein the sampling includes sampling a first portion of the data during an odd phase of the clock signal and sampling a second portion of the data during an even phase of the clock signal.