Single and double-gate pseudo-fet devices for semiconductor materials evaluation

Abstract

Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.

1 . A method for producing a test device for silicon-on-insulator (SOI) material comprising: 
 a) providing a protective mask layer in the shape of an array of isolated mesas over a Si surface of the SOI material;    b) removing Si material not protected by the protective mask layer to form an array of isolated Si mesas in the Si surface;    c) removing the protective mask layer from the array of isolated Si mesas in the Si surface; and    d) forming a pair of electrodes within each Si mesa of the array of isolated Si mesas by depositing one or more metal layers on each Si mesa.    
   
   
       2 . The method of  claim 1 , including forming the array of isolated Si mesas on a top Si surface of the SOI material, and depositing a metal layer on a bottom Si surface of the SOI material.  
   
   
       3 . The method of  claim 1 , wherein the step of depositing deposits one or more metal layers from the group consisting of Al, Er, Gd, Nd, Ti, Y, Ag, Au, Cr, Cu, Ni and Pt.  
   
   
       4 . The method of  claim 1 , further including the step of irradiating a Si surface of the test device with light having a wavelength shorter than the bandgap wavelength of the Si surface.  
   
   
       5 . A process for creating offset multiple layers of source and drain metal electrodes in an FET device test structure comprising: 
 a) positioning a patterned shadow mask separated from the surface of the test structure by a distance of at least 0.5 millimeters;    b) depositing a first metal electrode of a metal having a low barrier height for electrons from a first metal source through the patterned shadow mask onto the test structure; and    c) depositing a second metal electrode of a metal having a low barrier height for holes from a second metal source through the patterned shadow mask onto the test structure.    
   
   
       6 . The process of  claim 5 , including depositing the first metal electrode from a group consisting of Al, Er, Gd, Nd, Ti and Y which has a low barrier height for electrons, and depositing the second metal electrode from a group consisting of Ag, Al, Au, Cr, Cu, Mg, Ni and Pt which has a low barrier height for holes.  
   
   
       7 . The process of  claim 5 , for creating offset multiple layers of source and drain metal electrodes in a single gate ring FET device test structure.  
   
   
       8 . The process of  claim 5 , for creating offset multiple layers of source and drain metal electrodes in a double gate ring FET device test structure.  
   
   
       9 . An FET device comprising a source electrode and a drain electrode, wherein each of the source electrode and the drain electrode comprises first and second metals which are formed contacting each other while being offset relative to each other, the first metal comprises an ohmic metal which has a low barrier height for electrons, and the second metal comprises an ohmic metal which has a low barrier height for holes, such that both electron and hole electrical properties can be measured from the offset metal electrodes.  
   
   
       10 . The FET device of  claim 9 , wherein the first metal comprises an ohmic metal from the group consisting of Al, Er, Gd, Nd, Ti and Y which has a low barrier height for electrons, and the second metal comprises an ohmic metal from the group consisting of Ag, Al, Au, Cr, Cu, Mg, Ni and Pt which has a low barrier height for holes.  
   
   
       11 . The FET device of  claim 9 , in a double gate FET.  
   
   
       12 . The FET device of  claim 9 , in a single gate FET.