Semiconductor device including recessed-channel-array mosfet having a higher operational speed

Abstract

A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the bottom of the recess. The first portion has an equivalent oxide thickness larger than the equivalent oxide thickness of the second portion to reduce the parasitic capacitance of the gate electrode.

1 . A semiconductor device comprising:
 a semiconductor substrate having a recess thereon; and   a MOSFET including a gate insulating film formed on a surface of said recess, and a gate electrode opposing said surface of said recess with an intervention of said gate insulating film,   wherein said gate insulating film includes a first portion in contact with a sidewall of said recess, and a second portion in contact with a bottom surface of said recess, and said first portion has an equivalent oxide thickness which is larger than an equivalent oxide thickness of said second portion.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein said first portion includes silicon oxide and said second portion includes silicon oxynitride. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein a portion of said gate electrode protruding from said recess has a width which is smaller than a width of a top opening of said recess. 
   
   
       4 . A method for manufacturing a semiconductor device including a recessed-channel-array MOSFET, comprising:
 forming a recess on a semiconductor substrate;   forming a silicon oxide film on a surface of said recess;   selectively nitriding a portion of said silicon oxide film in contact with a bottom of said recess;   forming a gate electrode having a bottom portion received within said recess via said silicon oxide film; and   forming source/drain regions in association with said gate electrode in a surface region of said semiconductor substrate.   
   
   
       5 . The method according to  claim 4 , wherein said selectively nitriding uses an anisotropic plasma-enhanced nitriding treatment or an ion-implantation of nitrogen. 
   
   
       6 . The method according to  claim 4 , wherein said forming of said silicon oxide film uses a radical oxidation treatment which oxidizes a surface of a silicon substrate. 
   
   
       7 . The method according to  claim 4 , wherein said forming of said gate electrode includes depositing a silicon layer on an entire surface of said semiconductor substrate including an internal of said recess, and removing a portion of said silicon layer on top of said semiconductor substrate to leave said silicon layer in said recess.