Split gate nonvolatile memory and manufacturing method of the same

Abstract

A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.

1 . A split gate nonvolatile memory cell comprising:
 a first diffusion region;   a second diffusion region; and   a channel region formed between said first and second diffusion regions, including a first channel region having a predetermined dopant concentration,   wherein said first channel region is positioned apart from said first and second diffusion regions.   
     
     
         2 . The split gate nonvolatile memory cell according to  claim 1 , further comprising:
 a floating gate opposed to said channel region across a first insulating film; and   a control gate opposed to said floating gate and said channel region across a second insulating film,   wherein said channel region further includes:
 a second region connected between said first channel region and said first diffusion region; and 
 a third region connected between said first channel region and said second diffusion region, 
   wherein said first channel region is opposed to a spacing between said control gate and said floating gate across at least one of said first and second insulating films.   
     
     
         3 . The split gate nonvolatile memory cell according to  claim 2 , wherein said first channel region has a dopant concentration higher than those of said second and third channel regions. 
     
     
         4 . The split gate nonvolatile memory cell according to  claim 1 , wherein said channel region further includes:
 a second region connected between said first channel region and said first diffusion region; and   a third region connected between said first channel region and said second diffusion region, and   wherein said first channel region has a dopant concentration higher than those of said second and third channel regions.   
     
     
         5 . A split gate nonvolatile memory cell, comprising:
 a first diffusion region;   a second diffusion region; and   a channel region,   wherein said channel region includes:
 a first channel region having a first dopant concentration; 
 a second channel region having a second dopant concentration, and 
 a third channel region formed at a position where said first and second channel regions are overlapped. 
   
     
     
         6 . The split gate nonvolatile memory cell according to  claim 5 , further comprising:
 a floating gate opposed to said channel region across a first insulating film; and   a control gate opposed to said floating gate and said channel region across a second insulating film,   wherein said first channel region is positioned under said control gate,   wherein said second channel region is positioned under said floating gate, and   wherein said third channel region is positioned opposed to a spacing between said control gate and said floating gate.   
     
     
         7 . The split gate nonvolatile memory cell according to  claim 6 , wherein a dopant concentration of said third channel region is what dopant concentrations of said first and second channel regions are added together. 
     
     
         8 . A split gate nonvolatile memory cell comprising:
 a first diffusion region;   a second diffusion region; and   a channel region formed between said first and second diffusion regions,   wherein said channel region includes:   a first channel region;   a second channel region which does not overlap said first channel region; and   a third channel region which does not overlap said first and second channel regions,   wherein said third channel region has a dopant concentration different from those of said first and second channel regions.   
     
     
         9 . The split gate nonvolatile memory cell according to  claim 8 , further comprising:
 a floating gate opposed to said channel region across a first insulating film; and   a control gate opposed to said channel region across a second insulating film,   wherein a side surface of said control gate is opposed to said floating gate across a third insulating film,   wherein said first channel region is positioned under said control gate across said first insulating film,   wherein said second channel region is positioned under said floating gate across said second insulating film, and   wherein said third channel region is positioned under said third insulating film.   
     
     
         10 . The split gate nonvolatile memory cell according to  claim 9 , wherein said third channel region has a dopant concentration higher than those of said first and second channel regions.