Method of fabricating a capacitor of a memory device

Abstract

A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.

1 - 13 . (canceled)  
   
   
       14 . A method of fabricating a capacitor of a memory device including a transistor structure, the method comprising: 
 a) providing an insulating layer including a trench;    b) depositing a metal and a metal oxide inside the trench, thereby forming a lower electrode; and    c) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.    
   
   
       15 . The method as claimed in  claim 14 , wherein forming the lower electrode further comprises: 
 partially filling the trench with the metal and filling the trench with the metal oxide.    
   
   
       16 . The method as claimed in  claim 15 , wherein partially filling the trench comprises providing the metal on a bottom and sides of the trench, with a recess remaining in the metal within the trench.  
   
   
       17 . The method as claimed in  claim 14 , further comprising removing a portion of the insulating material.  
   
   
       18 . The method as claimed in  claim 14 , further comprising, prior to forming the insulating layer: 
 sequentially forming an adhesion layer and a second insulating layer, wherein removing the insulating material exposes the adhesion layer.    
   
   
       19 . The method of  claim 18 , wherein sequentially forming the ferroelectric layer comprises providing a ferroelectric material on the adhesion layer.  
   
   
       20 . The method of  claim 19 , wherein sequentially forming the ferroelectric layer further comprises removing portions of the ferroelectric material from the adhesion layer, in a direction parallel to the adhesion layer.  
   
   
       21 . A method of fabricating a capacitor of a memory device including a transistor structure, the method comprising: 
 forming a lower electrode electrically coupled to a doping region of the transistor structure, the lower electrode including a metal electrode and a metal oxide electrode;    forming a ferroelectric layer covering a top surface of the lower electrode and extending along a side of the lower electrode; and    forming an upper electrode on the ferroelectric layer.    
   
   
       22 . The method as claimed in  claim 21 , wherein the metal electrode protrudes from the transistor structure, further comprising forming a vertical trench in the metal electrode and the metal oxide electrode is formed in a vertical trench of the metal electrode.  
   
   
       23 . The method as claimed in  claim 21 , wherein the lower electrode is cylindrical.  
   
   
       24 . The method as claimed in  claim 21 , further comprising forming an oxidation stop layer between the transistor structure and the lower electrode.  
   
   
       25 . The method as claimed in  claim 24 , wherein the oxidation stop layer comprises at least one of titanium nitride (TiN) and titanium aluminum nitride (TiAlN).  
   
   
       26 . The method as claimed in  claim 21 , further comprising forming an insulating layer around a lower lateral portion of lower electrode and on the transistor structure.  
   
   
       27 . The method as claimed in  claim 26 , further comprising forming an adhesion layer on the upper surface of the insulating layer, the adhesion layer also surrounding a lower lateral portion of the lower electrode.  
   
   
       28 . The method as claimed in  claim 27 , wherein the ferroelectric layer is on an upper surface of the adhesion layer, the ferroelectric layer covering both a top surface and an upper lateral portion of the lower electrode.  
   
   
       29 . The method as claimed in  claim 27 , wherein the adhesion layer is composed of a material including at least one selected from the group consisting of titanium (Ti), titanium nitride (TiN), titanium dioxide (TiO 2 ), and titanium aluminum nitride (TiAlN).  
   
   
       30 . The method as claimed in  claim 26 , wherein the lower electrode is cylindrical.  
   
   
       31 . The method as claimed in  claim 26 , wherein the metal electrode protrudes from the transistor structure and the metal oxide electrode is formed in a vertical trench of the metal electrode.  
   
   
       32 . The method as claimed in  claim 26 , further comprising forming an oxidation stop layer between the transistor structure and the lower electrode.  
   
   
       33 . The method as claimed in of  claim 32 , wherein the oxidation stop layer comprises at least one of titanium nitride (TiN) and titanium aluminum nitride (TiAlN).