Dual trench isolation for cmos with hybrid orientations

Abstract

The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

1 . A semiconductor structure comprising: 
 a hybrid oriented substrate comprising a first device region having a first crystallographic orientation and a second device region having a second crystallographic orientation which differs from the first crystallographic orientation;    a first trench isolation region of a first depth separating said first device region from said second device region;    a plurality of second trench isolation regions of a second depth which is shallower than the first depth located in each of said first and second device regions; and    first semiconductor devices of a first polarity located in said first semiconductor device region and second semiconductor devices of a second polarity that differs from the first polarity located in said second semiconductor device region, wherein said first semiconductor devices are separated from said second semiconductor devices by said first trench isolation regions and said plurality of second trench isolation regions separate like-kind devices.    
   
   
       2 . The semiconductor structure of  claim 1  wherein the first crystallographic orientation is (110) and the second crystallographic orientation is (100).  
   
   
       3 . The semiconductor structure of  claim 2  wherein said first semiconductor devices are pFETs and second semiconductor devices nFETs.  
   
   
       4 . The semiconductor structure of  claim 1  wherein the first crystallographic orientation is (100) and the second crystallographic orientation is (110).  
   
   
       5 . The semiconductor structure of  claim 4  wherein said first semiconductor devices are nFETs and the second semiconductor devices are pFETs.  
   
   
       6 . The semiconductor structure of  claim 1  wherein the second device region includes a regrown semiconductor material located atop a first semiconductor layer, said regrown semiconductor material having the same crystallographic orientation as the first semiconductor layer.  
   
   
       7 . The semiconductor structure of  claim 6  wherein said regrown semiconductor material is a Si-containing semiconductor.  
   
   
       8 . The semiconductor structure of  claim 1  wherein said hybrid oriented substrate comprises a first bottom semiconductor layer having a first crystallographic orientation and a second upper semiconductor layer having a second crystallographic orientation which is different from the first crystallographic orientation, wherein said first and second semiconductor layers are separated from each other by a conductive bonding interface.  
   
   
       9 . The semiconductor structure of  claim 1  wherein said first trench isolation region is a spacer that is located within an opening of a hybrid substrate comprising a second upper semiconductor layer and a first bottom semiconductor layer, said semiconductor layers are separated from each other by a bonding interface and said opening exposing a surface of said first bottom semiconductor layer.  
   
   
       10 . The semiconductor structure of  claim 9  wherein said spacer is a single spacer or multiple spacers.  
   
   
       11 . A method of fabricating a semiconductor structure comprising: 
 providing a hybrid substrate comprising a first lower semiconductor layer of a first crystallographic orientation and a second upper semiconductor layer of a second crystallographic orientation which differs from the first crystallographic orientation, wherein a conductive bonding interface separates said semiconductor layers from each other;    providing at least one opening of a first depth in said hybrid substrate which exposes said first lower semiconductor layer;    forming a spacer within said at least one opening having said first depth;    regrowing a semiconductor material on said exposed first lower semiconductor layer, said semiconductor material having said first crystallographic orientation;    planarizing said semiconductor material to an upper surface of said second upper semiconductor layer to provide a structure having at least two coplanar surfaces of different crystallographic orientation; and    forming trench isolation regions having a second depth which is shallower than the first depth of said opening in said at least two coplanar surfaces, wherein said spacer provides isolates between the coplanar surfaces of different crystallographic orientations.    
   
   
       12 . The method of  claim 11  wherein said providing said hybrid substrate comprising a bonding process.  
   
   
       13 . The method of  claim 12  wherein said bonding comprising contacting said two semiconductor layers at nominal room temperature, optionally applying an external force and optionally annealing.  
   
   
       14 . The method of  claim 12  wherein said bonding process comprises treating a surface of at least one of the semiconductor layers to provide a hydrophobic or hydrophilic surface for bonding.  
   
   
       15 . The method of  claim 11  further comprising forming first semiconductor devices of a first polarity in said first device region and forming second semiconductor devices of a second polarity that differs from said first polarity in said second device region.  
   
   
       16 . The method of  claim 15  wherein said first semiconductor devices comprise nFETs and the second semiconductor devices comprise pFETs, said nFETs are located on a (100) crystallographic surface and said pFETs are located on a (110) crystallographic surface.  
   
   
       17 . The method of  claim 15  wherein said first semiconductor devices comprise pFETs and the second semiconductor devices comprise nFETs, said nFETs are located on a (100) crystallographic surface and said pFETs are located on a (110) crystallographic surface.