Fin Field-Effect Transistor and Method for Fabricating a Fin Field-Effect Transistor

Abstract

A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.

1 . An integrated circuit comprising: 
 an insulating layer;    a first source/drain portion and a second source/drain portion; and    a channel disposed between the first and second source/drain portions,    wherein the channel is disposed in a fin disposed over the insulating layer, and wherein an upper surface of the first and second source/drain portions is disposed at a higher height than an upper surface of the channel, the height being measured with respect to an upper surface of the insulating layer.    
   
   
       2 . The integrated circuit of  claim 1 , wherein at least one of the first and second source/drain portions comprises polysilicon.  
   
   
       3 . The integrated circuit of  claim 1 , wherein at least one of the first and second source/drain portions comprises a silicide containing a metal.  
   
   
       4 . The integrated circuit of  claim 1 , wherein the fin includes silicon.  
   
   
       5 . The integrated circuit of  claim 1 , further comprising a substrate beneath the insulating layer.  
   
   
       6 . An integrated circuit comprising: 
 an insulating layer;    a first source/drain portion and a second source/drain portion;    a channel disposed between the first and second source/drain portions;    a gate electrode adjacent the channel; and    an intermediate layer disposed between the channel and the first and second source/drain portions, respectively,    wherein the channel is disposed in a fin disposed over the insulating layer, and wherein the first and second source/drain portions are self-aligned with respect to the gate electrode.    
   
   
       7 . The integrated circuit of  claim 6 , wherein at least one of the first and second source/drain portions comprises polysilicon.  
   
   
       8 . The integrated circuit of  claim 6 , wherein at least one of the first and second source/drain portions comprises a silicide containing a metal.  
   
   
       9 . The integrated circuit of  claim 6 , wherein the fin includes silicon.  
   
   
       10 . An integrated circuit comprising: 
 an insulating layer;    a first source/drain portion and a second source/drain portion; and    a channel disposed between the first and second source/drain portions,    wherein the channel is disposed in a fin disposed over the insulating layer, and wherein a width of the first or second source/drain portion is larger than a width of the fin, the widths being measured perpendicularly with respect to a line connecting the first and second source/drain portions.    
   
   
       11 . The integrated circuit of  claim 10 , further comprising an intermediate layer disposed between the channel and the first and second source/drain portions, respectively.  
   
   
       12 . The integrated circuit of  claim 10 , wherein at least one of the first and second source/drain portions comprises polysilicon.  
   
   
       13 . The integrated circuit of  claim 10 , wherein at least one of the first and second source/drain portions comprises a silicide containing a metal.  
   
   
       14 . The integrated circuit of  claim 10 , wherein the fin includes silicon.  
   
   
       15 . An integrated circuit comprising: 
 an insulator layer;    a fin disposed over the insulator layer;    a first source/drain region and a second source/drain region disposed outside the fin over the insulator layer, the first and/or second source/drain region being formed from a material with metallic conductivity;    a Schottky barrier disposed between the first source/drain region and the fin and between the second source/drain region and the fin; and    a gate disposed adjacent a channel portion of the fin, the channel portion providing a current path between the first source/drain region and the second source/drain region.    
   
   
       16 . The integrated circuit of  claim 15 , further comprising a diffusion barrier disposed between the first source/drain region and the fin and between the second source/drain region and the fin.  
   
   
       17 . The integrated circuit of  claim 15 , wherein the gate extends substantially along the entire height of at least a part of the fin.  
   
   
       18 . The integrated circuit of  claim 15 , further comprising a substrate, wherein the insulator layer overlies the substrate.  
   
   
       19 . The integrated circuit of  claim 15 , wherein the material with metallic conductivity comprises a silicide.  
   
   
       20 . The integrated circuit of  claim 19 , wherein the material with metallic conductivity comprises a material selected from the group consisting of platinum silicide, platinum germanium silicide and erbium silicide.