Clock control circuit and integrated circuit

Abstract

A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.

1 . A clock control circuit for supplying a clock signal to a target circuit in accordance with a system clock signal, characterized in that: 
 a valid output instruction signal from the target circuit is applied to circuitry which generates a clock output enable signal that is used in determining when the clock signal is applied to the target circuit.    
   
   
       2 . A clock control circuit for supplying a clock signal to a target circuit according to  claim 1  and further wherein the circuitry which generates the clock output enable also receives a valid input signal flag.  
   
   
       3 - 7 . (canceled)  
   
   
       8 . A method for selectively applying a clock signal to a target circuit comprising: 
 generating a clock signal;    applying the clock signal to a target circuit;    transmitting a valid output instruction signal from the target circuit to circuitry which generates a clock output enable signal; and    applying the clock output enable signal to circuitry which selectively transmits the clock signal to the target circuit.    
   
   
       9 . The method for selectively applying a clock signal to a target circuit of  claim 8 , further comprising applying a valid input indication signal to the circuitry which generates the clock output enable signal.