LSI design method and verification method

Abstract

An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

1 - 7 . (canceled)  
   
   
       8 . A method for verifying an LSI, comprising the step of verifying a circuit operation for circuit design data encrypted together with a reference operation model, the verifying step including the steps of 
 decoding the encrypted circuit design data into actual design data and the reference operation model,    conducting simulation for the actual design data to obtain an actual output value, conducting simulation for the reference operation model to obtain an expected output value, and    comparing the actual output value with the expected output value to output a comparison result.    
   
   
       9 . A method for verifying an LSI, comprising the step of verifying a circuit operation for circuit design data encrypted together with protocol definition, the verifying step including the steps of 
 decoding the encrypted circuit design data into actual design data and the protocol definition,    conducting simulation for the actual design data to obtain an actual output value, and    comparing the actual output value with the protocol definition to output a comparison result.    
   
   
       10 . A method for verifying an LSI, comprising the step of verifying encrypted circuit design data by simulation, wherein the verifying step limits the simulation conducted by unauthorized access.  
   
   
       11 . The method according to  claim 10 , wherein the verifying step includes the steps of 
 decoding the encrypted circuit design data into actual design data,    conducting simulation for the actual design data,    counting prescribed limitation information in the simulation, and limiting the simulation when a count value exceeds an upper limit.    
   
   
       12 . The method according to  claim 11 , wherein the prescribed limitation information includes at least one of an execution step of the simulation, execution time of the simulation, a number of toggles of a specific signal within a circuit, and combination of inputs to the circuit.  
   
   
       13 . The method according to  claim 12 , wherein the prescribed limitation information is randomly selected.  
   
   
       14 . The method according to  claim 10 , wherein the verifying step includes the steps of 
 decoding the encrypted circuit design data into actual design data, conducting simulation for the actual design data,    checking in the simulation whether a prescribed protocol restriction condition is violated or not, and    limiting the simulation if the prescribed protocol restriction condition is violated.    
   
   
       15 . The method according to  claim 14 , wherein the prescribed protocol restriction condition includes at least one of an input protocol and an in-operation protocol.  
   
   
       16 . The method according to  claim 15 , wherein the prescribed protocol restriction condition is randomly selected.  
   
   
       17 . The method according to  claim 11 , wherein the limitation includes at least one of: discontinuing the simulation, reducing a simulation execution speed, and executing the simulation in an abnormal manner; outputting no simulation result; and producing no data or key to be passed to a following step.  
   
   
       18 . A method for verifying an LSI, comprising the steps of: 
 encrypting circuit design data including a check circuit for checking for unauthorized access in simulation; and    verifying the encrypted circuit design data by simulation, wherein the verifying step operates the check circuit so as to limit the simulation conducted by unauthorized access.    
   
   
       19 . The method according to  claim 18 , wherein the check circuit checks in the simulation whether a count value of prescribed limitation information exceeds an upper limit or not.  
   
   
       20 . The method according to  claim 18 , wherein the check circuit checks in the simulation whether a protocol restriction condition is violated or not.  
   
   
       21 . A method for designing an LSI, comprising the steps of: 
 extracting timing information from provided circuit design data;    converting the circuit design data into encrypted design data according to a prescribed conversion rule so as to match only the extracted timing information, and adding a buffer to at least one logic gate;    adjusting a size of the added buffer for the encrypted design data; and    by using the prescribed conversion rule as a key, decoding the encrypted design data subjected to the adjustment of the buffer size.    
   
   
       22 . A method for designing an LSI, comprising the step of decoding circuit design data encrypted together with a circuit for determining a unique ID into actual design data and the unique-ID determination circuit, the step including the step of defining a correct value in the unique-ID determination circuit by using an input unique parameter.  
   
   
       23 . The method according to  claim 14 , wherein the limitation includes at least one of: discontinuing the simulation, reducing a simulation execution, speed, and executing the simulation in an abnormal manner; outputting no simulation result; and producing no data or key to be passed to a following step.