Novel Metallization Scheme and Method of Manufacture Therefor

Abstract

The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme ( 300 ) includes a protective layer ( 320 ) located over a substrate ( 310 ), and a conductive layer ( 330 ) located over the protective layer ( 320 ). The metallization scheme ( 300 ) further includes a stress-reducing low-modulus material ( 340 ) located between the protective layer ( 320 ) and the conductive layer ( 330 ).

1 . A method for manufacturing a semiconductor device, comprising: 
 providing a substrate having a first modulus of elasticity;    forming transistor components at the surface of the substrate;    disposing dielectric layers over the transistor components;    forming interconnect structures within the dielectric layers, connecting the transistor components;    disposing a protective layer over the dielectric layers and the interconnect structures, having a top surface;    patterning a low-modulus structure of material having a second modulus of elasticity lower than the first modulus of elasticity in contact with the top surface of the protective layer; and    forming a conductive layer having a long expansive of uninterrupted portion positioned perpendicular to and contacting the patterned structure of low-modulus material and in contact with the top surface of the protective layer and in contact with the interconnect structure.    forming a protective layer over a substrate; the substrate having a modulus of elasticity;    forming a material over the protective layer; the material having a modulus of elasticity less than the modulus of elasticity of the substrate;    forming a conductive layer over the protective layer.    
   
   
       2 . The method of  claim 1 , wherein disposing a protective layer comprising disposing a copper layer.  
   
   
       3 . The method of  claim 1 , wherein the transistor components form a part of an integrated circuit, and the conductive layer covers over 60% of the integrated circuit.  
   
   
       4 . The method of  claim 3 , wherein the conductive layer covers over 80% of the integrated circuit.  
   
   
       5 . The method of  claim 1 , wherein the conductive layer forms a interdigitating pattern.  
   
   
       6 . The method of  claim 1 , wherein the low-modulus material forms a linear pattern.  
   
   
       7 . The method of  claim 6 , wherein the lines of the low-modulus material run substantially perpendicular to the digits of the conductive layer.  
   
   
       8 . The method of  claim 1 , wherein the low-modulus material comprises a material selected from the group consisting of polybenzoxazole, benzocyclobutene, polyimides, silicone-modified polyimides, flexible epoxy, and silicon-modified flexible epoxy.  
   
   
       9 . The method of  claim 1 , wherein the low-modulus matereial comprises air.  
   
   
       10 . The device of  claim 1  wherein the protective layer includes oxynitride.  
   
   
       11 . The method of  claim 1 , wherein the protective layer includes oxynitride.