Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device

Abstract

A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.

1 . A method of forming a CMOS semiconductor device, the method comprising: 
 forming first wells of first conductivity type in a semiconductor substrate;    forming second wells of second conductivity type in the semiconductor substrate;    forming third wells of second conductivity type in the semiconductor substrate, the third well being connected to the second well and disposed under a region of the first wells;    forming a first conductivity type MOSFETs including source/drain of first conductivity type in the second well; and    forming second conductivity type MOSFETs including source/drain of second conductivity type in the first well.    
   
   
       2 . The circuit of  claim 1 , wherein the forming of the first wells is performed before or after the second wells are formed, 
 wherein the forming of the third wells is performed before or after the first and second wells are formed, and    wherein the forming of the first conductivity type MOSFETs is performed before or after the second conductivity type MOSFETs are formed.    
   
   
       3 . The method of  claim 1 , before or after the third wells are formed, further comprising: 
 forming a fourth well of first conductivity type in a semiconductor substrate under and between the third wells.    
   
   
       4 . The method of  claim 1 , wherein the first conductivity type is P type and the second conductivity type is N type.  
   
   
       5 . The method of  claim 1 , after the first MOSFET and the second MOSFET are formed, further comprising: 
 forming an interconnection for connecting source/drain terminals and the gate terminals of the first and second MOSFETs so as to make the first MOSFET and the second MOSFET compose a CMOS inverter.    
   
   
       6 . The method of  claim 4 , wherein the third wells are formed under the source/drain terminal of the first MOSFET connected by the interconnection.  
   
   
       7 . A method of forming an SRAM device, comprising: 
 forming deep N-wells in a predetermined region of a semiconductor substrate;    forming P-wells disposed on the deep N-well in the semiconductor substrate and connected to the semiconductor substrate between the deep N-wells;    forming N-wells disposed on the deep N-well in the semiconductor substrate and connected to the deep N-well; and    forming load transistors of the SRAM at the P-well and forming driver transistors and transfer transistors of the SRAM at the N-well.    
   
   
       8 . The method of  claim 6 , wherein the deep N-well is formed at a region under both a drain of the driver transistor and the P-well.  
   
   
       9 . The method of  claim 6 , wherein before the deep N-well is formed, further comprising: 
 forming a deep P-well at a substantially entire surface of the semiconductor substrate; and    wherein the deep P-well is connected to the P-well between the deep N-wells.