Efficient space-time adaptive processing (stap) filter for global positioning system (gps) receivers

Abstract

A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed. Advantageously, embodiments can efficiently null a relatively large number of jammers at a relatively low cost and with relatively low operating power.

1 . A method of reusing data in a GPS space-time adaptive processing (STAP) filter, the method comprising: 
 calculating Fourier Transforms of input samples for GPS antenna elements;    using the calculated Fourier Transforms to compute Fourier Transform correlation at least for computation of cross-power spectra among the GPS antenna elements; and    reusing the same calculated Fourier Transforms to compute Fourier Transform convolution for beamforming.    
     
     
         2 . The method as defined in  claim 1 , wherein calculating Fourier Transforms comprises calculating Fast Fourier Transforms.  
     
     
         3 . The method as defined in  claim 1 , wherein the antenna element is a GPS antenna element, the cross-power spectra is for at least the GPS antenna element, and the beamforming is for the GPS antenna element.  
     
     
         4 . An apparatus comprising: 
 Fourier Transform processors configured to compute Fourier Transforms of data samples from two or more antennas;    a beamformer coupled to outputs of the Fourier Transform processors, wherein the beamformer computes convolution with the Fourier Transforms of the data samples; and    a correlation circuit in communication with the outputs of the same Fourier Transform processors, wherein the correlation circuit is configured to compute correlation among the two or more antennas at least for computation of cross-power spectra with the same Fourier Transforms of the data samples.    
     
     
         5 . The apparatus as defined in  claim 4 , wherein the Fourier Transform processor comprises a Fast Fourier Transform processor.  
     
     
         6 . The apparatus as defined in  claim 4 , wherein the apparatus further comprises a global positioning system (GPS) receiver.  
     
     
         7 . The apparatus as defined in  claim 4 , wherein the data samples are from GPS antennas, and the computed correlation is of the GPS antennas.  
     
     
         8 . A method of computing a Fast Fourier Transform (FFT), the method comprising: 
 receiving input samples in natural order;    providing the input samples directly to an FFT pipeline without a delay stage that implements filling of a constant, wherein the direct loading to the FFT pipeline includes the constant loading; and    processing the input samples through the FFT pipeline.    
     
     
         9 . The method as defined in  claim 8 , wherein the constant is zero.  
     
     
         10 . The method as defined in  claim 8 , wherein the input samples are provided directly to the multiplier and to the switch of an FFT pipeline without a delay stage that implements filling of a constant.  
     
     
         11 . The method as defined in  claim 8 , wherein the FFT pipeline is configured to compute an FFT with decimation in frequency.  
     
     
         12 . A pipelined circuit for computation of a Fourier Transform, the pipelined circuit comprising: 
 a multiplier with an input coupled to an input terminal, wherein the multiplier is configured to multiply input samples with twiddle factors;    a first delay stage with an input coupled to an output of the multiplier;    a switch having a first input coupled to the input terminal and a second input coupled to an output of the first delay stage, wherein the switch is configured to provide a straight connection in a first state and a cross connection in a second state;    a second delay stage with an input coupled to a first output of the switch; and    a butterfly stage with a first input coupled to a second output of the switch and a second input coupled to an output of the second delay stage, wherein the butterfly stage is configured to couple to another stage of the pipelined circuit for processing of the Fourier Transform.    
     
     
         13 . The pipelined circuit as defined in  claim 6 , further comprising a second stage, wherein the second stage comprises: 
 a second multiplier with an input coupled to a difference output of the butterfly stage, wherein the second multiplier is configured to multiply data from the difference output with twiddle factors;    a third delay stage with an input coupled to an output of the second multiplier;    a second switch with a first input coupled to a sum output of the butterfly stage and a second input coupled to an output of the third delay stage, wherein the second switch is configured to provide a straight connection in a first state and a cross connection in a second state;    a fourth delay stage with an input coupled to a first output of the second switch; and    a second butterfly stage with a first input coupled to a second output of the second switch and a second input coupled to an output of the fourth delay stage, wherein outputs of the second butterfly stage are provided to a subsequent stage for further processing of the Fourier Transform.    
     
     
         14 . The pipelined circuit as defined in  claim 6 , wherein the pipelined circuit is embodied in a GPS receiver.