Balanced sense amplifier circuits

Abstract

Structures and methods are disclosed for operating Balanced Sense Amplifier Circuits. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

1 . A digital circuit, comprising: 
 (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively;    (b) a control circuit, which is electrically coupled to the first and second transistor bodies; and    (c) a testing circuit, which is electrically coupled to the control circuit and the enable device of the reading circuit, 
 wherein the testing circuit is capable of determining whether (i) strengths of the first and second transistors are different or (ii) the first and second transistors are of equal strength, and  
 wherein, in response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first or second transistor body.  
   
   
   
       2 . The digital circuit of  claim 1 , 
 wherein, in response to the testing circuit determining that the strengths of the first and second transistors are different, the testing circuit is further capable of determining whether (i) the first transistor is stronger than the second transistor or (ii) the second transistor is stronger than the first transistor, and    wherein, in response to the testing circuit determining that the first transistor is stronger than the second transistor, the control circuit is capable of raising the voltage of the first or second transistor body.    
   
   
       3 . The digital circuit of  claim 1 , further comprising a cell array, which includes a first cell column, 
 wherein the first cell column comprises a bit line pair, and    wherein the bit line pair is electrically coupled to the first and second transistor gate electrodes.    
   
   
       4 . The digital circuit of  claim 1 , wherein the reading circuit further includes a third transistor and a fourth transistor, 
 wherein the first and third transistors are electrically coupled in series between a first operating voltage and a second operating voltage,    wherein the second and fourth transistors are electrically coupled in series between the first and second operating voltages, and    wherein the first, second, third, and fourth transistors form a latch. (possibly to narrow of a definition of a sense amp. Other types exist)    
   
   
       5 . The digital circuit of  claim 4 , 
 wherein the first and third transistors are electrically coupled together to form a first inverter, which includes a first inverter input node and a first inverter output node, such that if the first inverter input node is low level, then the first inverter causes the first inverter output node to be high level,    wherein the second and fourth transistors are electrically coupled together to form a second inverter, which includes a second inverter input node and a second inverter output node, such that if the second inverter input node is low level, then the second inverter causes the second inverter output node to be high level,    wherein the second inverter input node is electrically coupled to the first inverter output node, and    wherein the second inverter output node is electrically coupled to the first inverter input node.    
   
   
       6 . The digital circuit of  claim 1 , 
 wherein the reading circuit further includes an enable transistor, and    wherein the enable transistor is capable of enabling the reading circuit, resulting in the testing circuit being capable of determining whether the strengths of the first and second transistors are different.    
   
   
       7 . A circuit adjusting method, comprising: 
 providing a digital circuit, which includes: 
 (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively,  
 (b) a control circuit, which is electrically coupled to the first and second transistor bodies, respectively, and  
 (c) a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit;  
   using the testing circuit to determine, for a first balanced determination round, whether strengths of the first and second transistors are different; and    in response to the testing circuit determining that the strengths of the first and second transistors are different, using the testing circuit to cause the control circuit to adjust the voltage of the first transistor body for a first time.    
   
   
       8 . The method of  claim 7 , 
 wherein said using the testing circuit to determine comprises using the testing circuit to determine, for the first balanced determination round, whether (i) the first transistor is stronger than the second transistor, (ii) the second transistor is stronger than the first transistor, or (iii) the first and second transistors are of equal strength, and    wherein said using the testing circuit to cause the control circuit to adjust the voltage of the first transistor body comprises using the testing circuit to cause the control circuit to raise the voltage of the first transistor body for a first time.    
   
   
       9 . The method of  claim 8 , further comprising, after said using the testing circuit to cause the control circuit to raise the voltage of the first transistor body for the first time is performed: 
 using the testing circuit to determine, for a second balanced determination round, whether (i) the first transistor is stronger than the second transistor, (ii) the second transistor is stronger than the first transistor, or (iii) the first and second transistors are of equal strength; and    in response to the testing circuit determining, for the second balanced determination round, that the first transistor is stronger than the second transistor, then using the testing circuit to cause the control circuit to raise the voltage of the first transistor body for a second time.    
   
   
       10 . The method of  claim 8 , further comprising, after said using the testing circuit to cause the control circuit to raise the voltage of the first transistor body for the first time is performed: 
 using the testing circuit to determine, for a second balanced determination round, whether (i) the first transistor is stronger than the second transistor, (ii) the second transistor is stronger than the first transistor, or (iii) the first and second transistors are of equal strength; and    in response to the testing circuit determining, for the second balanced determination round, that the second transistor is stronger than the first transistor, then keeping the voltage of the first transistor body unchanged.    
   
   
       11 . The method of  claim 7 , wherein said using the testing circuit to determine, for the first balanced determination round, comprises using the testing circuit to perform N reading evaluation rounds, 
 wherein N is a positive integer,    wherein each of the N reading evaluation rounds comprises: 
 equalizing the first and second transistor gate electrodes;  
 enabling the reading circuit; and  
 determining whether the reading circuit reads a 1 or a 0,  
   wherein the reading circuit is considered reading a 1 if the first transistor gate electrode is at high level and the second transistor gate electrode is at low level, and wherein the reading circuit is considered reading a 0 if the first transistor gate electrode is at low level and the second transistor gate electrode is at high level.    
   
   
       12 . The method of  claim 11 , further comprising, after said using the testing circuit to performing the N reading evaluation rounds is performed, in response to a first number of times the reading circuit reads a 1 being greater than a second number of times the reading circuit reads a 0 by a pre-specified number, determining that the first transistor is stronger than the second transistor.  
   
   
       13 . A memory device, comprising: 
 (a) a memory cell array comprising N columns, wherein N is a positive integer greater than 1;    (b) N sense amp circuits, wherein the N sense amp circuits are electrically coupled one-to-one to the N columns of the memory cell array, each of the N sense amp circuits comprising a first transistor and a second transistor, wherein the first and second transistors include: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively;    (c) N control circuits, wherein the N control circuits are electrically coupled one-to-one to the N sense amp circuits, and wherein each of the N control circuits is electrically coupled to the first and second transistor bodies of the respective sense amp circuit; and    (d) N testing circuits, wherein the N testing circuits are electrically coupled one-to-one to the N control circuits and the N sense amp circuits, 
 wherein each of the N testing circuits is capable of determining whether (i) strengths of the first and second transistors of the respective sense amp circuit are different or (ii) the first and second transistors of the respective sense amp circuit are of equal strength, and  
 wherein, in response to the testing circuit determining that the strengths of the first and second transistors of the respective sense amp circuit are different, the respective control circuit is capable of adjusting the voltage of the first transistor body of the respective sense amp circuit.  
   
   
   
       14 . The memory device of  claim 13 , 
 wherein, in response to each of the N testing circuits determining that the strengths of the first and second transistors of the respective sense amp circuit are different, each of the N testing circuits is further capable of determining whether (i) the first transistor of the respective sense amp circuit is stronger than the second transistor of the respective sense amp circuit or (ii) the second transistor of the respective sense amp circuit is stronger than the first transistor of the respective sense amp circuit, and    wherein, in response to each of the N testing circuits determining that the first transistor of the respective sense amp circuit is stronger than the second transistor of the respective sense amp circuit, the respective control circuit is capable of raising the voltage of the first transistor body of the respective sense amp circuit.    
   
   
       15 . The memory device of  claim 13 , 
 wherein each of the N sense amp circuits comprises a third transistor and a fourth transistor,    wherein the first and third transistors of each of the N sense amp circuits are electrically coupled in series between a first operating voltage and a second operating voltage,    wherein the second and fourth transistors of each of the N sense amp circuits are electrically coupled in series between the first and second operating voltages, and    wherein the first, second, third, and fourth transistors of each of the N sense amp circuits form a latch.    
   
   
       16 . The memory device of  claim 15 , 
 wherein the first and third transistors of each of the N sense amp circuits are electrically coupled together to form a first inverter, which includes a first inverter input node and a first inverter output node, such that if the first inverter input node is low level, then the circuit causes the first inverter output node to be high level,    wherein the second and fourth transistors of each of the N sense amp circuits are electrically coupled together to form a second inverter, which includes a second inverter input node and a second inverter output node, such that if the second inverter input node is low level, then the circuit causes the second inverter output node to be high level,    wherein the second inverter input node is electrically coupled to the first inverter output node, and    wherein the second inverter output node is electrically coupled to the first inverter input node.