Fabrication methods for compressive strained-silicon and transistors using the same

Abstract

Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.

1 . A transistor fabricated by a fabrication method for compressive strained-silicon, the transistor comprising: 
 a strain inducing layer formed by ion implantation and high temperature processing;    a channel region on the strain inducing layer, whereby compressive strained-silicon is formed therein;    source/drain regions adjacent to two ends of the channel region;    a gate dielectric layer on the channel region; and    a gate on the gate dielectric layer.    
   
   
       2 . The transistor as claimed in  claim 1 , wherein the ions implanted into the silicon-containing substrate are hydrogen.  
   
   
       3 . The transistor as claimed in  claim 2 , wherein the dosage of implantation is between 1E14 cm −2  and 1E17 cm −2 .  
   
   
       4 . The transistor as claimed in  claim 2 , wherein implant depth is between 3 nm and 10 μm.  
   
   
       5 . The transistor as claimed in  claim 2 , wherein the silicon-containing substrate is a single crystal, polycrystalline, amorphous silicon, SiGe, or silicon on insulator (SOI) substrate.  
   
   
       6 . The transistor as claimed in  claim 5 , wherein the silicon-containing substrate is attached or bonded to other substrate or film.  
   
   
       7 . The transistor as claimed in  claim 2 , wherein the channel region is an asymmetrical compressively strained channel.  
   
   
       8 . The transistor as claimed in  claim 2 , wherein high temperature processing is performed at between 25° C. and 1200° C.  
   
   
       9 . The transistor as claimed in  claim 2 , wherein the high temperature processing lasts from several seconds to hours.  
   
   
       10 . The transistor as claimed in  claim 2 , wherein the source drain regions are formed using metal, silicide, SiGe.  
   
   
       11 . The transistor as claimed in  claim 2 , wherein the gate dielectric layer is silicon-oxide, HfO 2 , Si 3 N 4 , Al 2 O 3  or other dielectric material with a dielectric constant higher than 3.9.  
   
   
       12 . The transistor as claimed in  claim 2 , wherein the gate is formed using metal, silicide, SiGe, poly-SiGe or polysilicon.  
   
   
       13 . A transistor fabricated by a fabrication method of compressive strained-silicon, the transistor comprising: 
 source/drain regions;    strain inducing layers, formed after ion implantation and high temperature processing, under the source/drain regions;    a channel region between the source/drain regions, whereby compressive strained-silicon is formed therein;    a gate dielectric layer on the channel region; and    a gate on the gate dielectric layer.    
   
   
       14 . The transistor as claimed in  claim 13 , wherein the ions implanted into the silicon-containing substrate are hydrogen.  
   
   
       15 . The transistor as claimed in  claim 14 , wherein the dosage of implantation is between 1E14 cm −2  and 1E17 cm −2 .  
   
   
       16 . The transistor as claimed in  claim 14 , wherein implant depth is between 3 nm and 10 μm.  
   
   
       17 . The transistor as claimed in  claim 14 , wherein the silicon-containing substrate is a single crystal, polycrystalline, amorphous silicon, SiGe, or silicon on insulator (SOI) substrate.  
   
   
       18 . The transistor as claimed in  claim 17 , wherein the silicon-containing substrate is attached or bonded to other substrate or film.  
   
   
       19 . The transistor as claimed in  claim 14 , wherein the channel region is an asymmetrical compressively strained channel.  
   
   
       20 . The transistor as claimed in  claim 14 , wherein high temperature processing is performed at between 25° C. and 1200° C.  
   
   
       21 . The transistor as claimed in  claim 14 , wherein the high temperature processing lasts from several seconds to hours.  
   
   
       22 . The transistor as claimed in  claim 14 , wherein the source drain regions are formed using metal, silicide, SiGe.  
   
   
       23 . The transistor as claimed in  claim 14 , wherein the gate dielectric layer is silicon-oxide, HfO 2 , Si 3 N 4 , Al 2 O 3  or other dielectric material with a dielectric constant higher than 3.9.  
   
   
       24 . The transistor as claimed in  claim 14 , wherein the gate is formed using metal, silicide, SiGe, poly-SiGe or polysilicon.