A test structure and method for detecting charge effects during semiconductor processing

Abstract

A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

1 . A test structure formed on a silicon substrate to measure charge status that results from a semiconductor processing step, comprising:
 a substrate;   a diffusion region formed in the substrate;   a gate electrode above the substrate and diffusion region; and   a charge trapping layer between the gate electrode and the substrate and diffusion region, the charge trapping layer configured to accumulate charge imparted during the semiconductor processing step.   
   
   
       2 . The test structure of  claim 1 , wherein the diffusion region and the gate electrode are metalized. 
   
   
       3 . The test structure of  claim 2 , further comprising interconnection leads coupled with the metalized gate electrode and diffusion region. 
   
   
       4 . The test structure of  claim 1 , wherein the charge trapping layer comprises a dielectric layer. 
   
   
       5 . The test structure of  claim 1 , wherein the charge trapping layer comprises an Oxide-Nitride-Oxide dielectric layer. 
   
   
       6 . The test structure of  claim 1 , wherein the charge trapping layer comprises an Oxide-Si-Oxide layer. 
   
   
       7 . The test structure of  claim 1 , wherein the charge trapping layer comprises a layer with high dielectric constant material. 
   
   
       8 . The test structure of  claim 7 , wherein the high dielectric constant material comprises any one of the materials of nitride, Al2O3, and Hf2O3 
   
   
       9 . The test structure of  claim 1 , wherein the substrate is a P-type silicon substrate. 
   
   
       10 . The test structure of  claim 9 , wherein the diffusion region is a N-type diffusion region. 
   
   
       11 . The test structure of  claim 1 , wherein the substrate is a N-type substrate. 
   
   
       12 . The test structure of  claim 1 , wherein the diffusion region is a P-type diffusion region. 
   
   
       13 . The test structure of  claim 1 , wherein the gate electrode comprises a poly-silicon layer. 
   
   
       14 . The test structure of  claim 1 , wherein the gate electrode comprises fingers. 
   
   
       15 . The test structure of  claim 1 , wherein the gate electrode comprises long lines. 
   
   
       16 . The test structure of  claim 1 , further comprising a partial oxide region. 
   
   
       17 . The test structure of  claim 1 , further comprising an oxide region, wherein the gate electrode is surrounded by the oxide region. 
   
   
       18 . The test structure of  claim 1 , comprising a plurality of diffusion regions separated by the gate electrode. 
   
   
       19 . The test structure of  claim 18 , wherein the charge trapping layer is configured to accumulate a charge over each of the plurality of diffusion regions. 
   
   
       20 . A method for measuring a charge status for a test structure formed on a silicon substrate that results form a semiconductor processing step, the method comprising:
 subjecting the test structure to the semiconductor processing step;   applying bias voltages to the test structure, the bias voltages configured to generate a gate induced drain leakage current in the test structure, the gate induced drain leakage current related to charge accumulated in the test structure during the semiconductor processing step.   
   
   
       21 . The method of  claim 20 , further comprising measuring the gate induced drain leakage current and determining a voltage threshold shift for the test structure based on the measured gate induced drain leakage current. 
   
   
       22 . The method of  claim 20 , further comprising measuring the gate induced drain leakage current and determining an antenna effect based on the measured gate induced drain leakage current. 
   
   
       23 . The method of  claim 20 , wherein the test structure comprises a gate electrode and a diffusion region, the method further comprising placing probes directly on the gate electrode and diffusion region and measuring a charge status using the probes. 
   
   
       24 . The method of  claim 20 , wherein the test structure comprises a gate electrode, a diffusion region and interconnection leads couple with the gate electrode and diffusion region, the method further comprising placing probes on the interconnection leads and measuring a charge status using the probes.