Inkjet printhead and method of manufacturing the same

Abstract

An inkjet printhead and a method of manufacturing the same are provided. The inkjet printhead includes a substrate; a plurality of heaters formed on an upper portion of the substrate for heating ink for generating bubbles; a plurality of metal-oxide semiconductor (MOS) field effect transistors (FETs) formed on the substrate for addressing the heaters and applying electric current to the heaters; first, second, and third interconnecting layers that are sequentially formed on the MOS FETs and electrically connected to each other for applying signals to the MOS FETs; a chamber layer for defining an ink chamber, which is filled with ink for ejection, on an upper portion of the heaters; and a nozzle layer having a nozzle, through which the ink is ejected, on an upper portion of the chamber layer.

1 . A method of manufacturing an inkjet printhead, comprising: 
 forming a plurality of metal-oxide semiconductor (MOS) field effect transistors (FETs) on a surface of a substrate;    forming first, second, and third interconnecting layers for applying signals to the MOS FETs, and heaters that are driven by the MOS FETs;    forming a chamber layer for defining an ink chamber, which is filled with ink for ejection, on an upper portion of the heaters; and    forming a nozzle layer having a nozzle, through which the ink is ejected, on an upper portion of the chamber layer.    
     
     
         2 . The method of  claim 1 , wherein in the second step of forming, the first, second, and third interconnecting layers are sequentially formed on the MOS FETs, and the heaters are formed on a lower surface of the third interconnecting layer.  
     
     
         3 . The method of  claim 1 , wherein the second step of forming further comprises: 
 forming a first interlayer dielectric on the MOS FETs, and forming the first interconnecting layer on the first interlayer dielectric;    forming a second interlayer dielectric on the first interconnecting layer, and forming the second interconnecting layer on the second interlayer dielectric;    forming a third interlayer dielectric on the second interconnecting layer, and forming the heaters on the third interlayer dielectric; and    forming the third interconnecting layer on the heaters.    
     
     
         4 . The method of  claim 3 , wherein the first, second, and third interlayer dielectrics comprise SiO2 or boron phosphorous silicate glass.  
     
     
         5 . The method of  claim 3 , wherein forming the first interconnecting layer comprises: 
 forming a contact hole, which exposes a source and a drain of the MOS FETs, in the first interlayer dielectric; and    depositing a metal material on an upper surface of the first interlayer dielectric so as to fill the contact hole, and patterning the deposited material.    
     
     
         6 . The method of  claim 3 , wherein forming the second interconnecting layer comprises: 
 forming a first via hole, which exposes a portion of the first interconnecting layer, in the second interlayer dielectric; and    depositing a metal material on an upper surface of the second interlayer dielectric so as to fill the first via hole, and patterning the deposited material.    
     
     
         7 . The method of  claim 3 , wherein forming the heaters comprises: 
 forming a second via hole, which exposes a portion of the second interconnecting layer, in the third interlayer dielectric; and    depositing a resistive heating material on the third interlayer dielectric and the exposed surface of the second interconnecting layer, and patterning the deposited material.    
     
     
         8 . The method of  claim 7 , wherein the resistive heating material comprises TaAl, TaN, or TiN.  
     
     
         9 . The method of  claim 3 , wherein forming the third interconnecting layer includes depositing a metal material on the upper surface of the heaters and patterning the deposited material.  
     
     
         10 . The method of  claim 1 , further comprising forming a passivation layer on the upper portion of the third interconnecting layer and the heaters.  
     
     
         11 . The method of  claim 10 , wherein the passivation layer comprises SiN.  
     
     
         12 . The method of  claim 10 , further comprising forming an anti-cavitation layer on an upper surface of the passivation layer, on which the ink chamber is located.  
     
     
         13 . The method of  claim 12 , wherein the anti-cavitation layer comprises Ta.  
     
     
         14 . The method of  claim 12 , wherein the anti-cavitation layer comprises Ti and TiN.