Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell

Abstract

A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.

1 . A method for forming a non-volatile memory cell, the method comprising: 
 forming a tunneling layer over a substrate surface;    forming a charge trapping layer disposed on the first insulating layer;    forming a blocking layer over the charge trapping layer;    etching the blocking layer, the charge trapping layer, and the tunneling layer to expose a first portion of the substrate and to form a substantially vertical edge structure including edges of the blocking layer, the charge trapping layer, and the tunneling layer;    forming a gate insulation layer on the first portion of the substrate surface to a thickness less than a thickness of the vertical edge structure;    forming a gate layer disposed on the gate insulation layer and the blocking layer, the gate layer having a first edge and a second edge; and    forming a source region and a drain region in the substrate substantially below the respective first and second edges of the gate layer.    
   
   
       2 . The method of  claim 1  wherein the first portion of the substrate is greater than one-half of a distance between the source region and the drain region.  
   
   
       3 . The method of  claim 1  wherein the first portion of the substrate is greater than two-thirds of a distance between the source region and the drain region.  
   
   
       4 . The method of  claim 1  wherein the first portion of the substrate is approximately three-fourths of a distance between the source region and the drain region.  
   
   
       5 . The method of  claim 1  wherein forming a charge trapping layer comprises forming a silicon nitride layer.  
   
   
       6 . The method of  claim 5  wherein the silicon nitride layer has a thickness of between about 40-80 Å.  
   
   
       7 . The method of  claim 1  wherein forming a charge trapping layer comprises forming a layer of nitride dots.  
   
   
       8 . The method of  claim 1  wherein forming a charge trapping layer comprises forming a layer of polysilicon dots.  
   
   
       9 . The method of  claim 1  wherein forming a charge trapping layer comprises forming an oxynitride layer.  
   
   
       10 . The method of  claim 1  wherein forming the tunneling layer comprises forming an oxynitride layer.  
   
   
       11 . The method of  claim 1  wherein forming the tunneling layer comprises forming a silicon dioxide layer.  
   
   
       12 . The method of  claim 1  wherein forming a gate layer comprises: 
 forming a layer of polysilicon material over the gate insulation layer and the blocking layer; and    etching the layer of polysilicon material.    
   
   
       13 . A method for forming a non-volatile memory cell, the method comprising: 
 forming a tunneling layer over a portion of a substrate surface, the substrate including a source region and a drain region;    forming a charge trapping layer over either the source region or the drain region, the charge trapping layer having a length limited so as to allow any electrons stored in the trapping layer during a programming process to be erased during an erasing process;    forming a blocking layer over the charge trapping layer;    forming a gate insulation layer on a portion of the substrate surface not covered by the tunneling layer; and    forming a gate layer disposed over the gate insulation layer and the blocking layer.    
   
   
       14 . The method of  claim 13  wherein a length of the charge trapping layer covered by the gate layer is less than one-half a distance from an edge of the drain region to an edge of the source region.  
   
   
       15 . The method of  claim 13  wherein a length of the charge trapping layer covered by the gate layer is less than one-fourth a distance from an edge of the drain region to an edge of the source region.  
   
   
       16 . The method of  claim 13  wherein forming a charge trapping layer comprises forming a silicon nitride layer.  
   
   
       17 . The method of  claim 13  wherein forming a charge trapping layer comprises forming a layer of nitride dots.  
   
   
       18 . The method of  claim 13  wherein forming a charge trapping layer comprises forming a layer of polysilicon dots.  
   
   
       19 . The method of  claim 13  wherein forming a charge trapping layer comprises forming an oxynitride layer.  
   
   
       20 . A method for forming a non-volatile memory cell, the method comprising: 
 forming a tunneling layer over a first portion, a second portion, and third portion of a substrate;    forming a charge trapping layer disposed on the tunneling layer;    forming a blocking layer on the charge trapping layer;    etching the blocking layer, the charge trapping layer, and the tunneling layer to expose the second portion of the substrate;    forming a gate insulation layer on the second portion of the substrate; and    forming a control gate disposed on the gate insulation layer and the blocking layers on the first and third portion of the substrate.    
   
   
       21 . The method of  claim 20  wherein the control gate has a first edge and a second edge, the method further comprising forming a source region and a drain region in the substrate substantially below the first edge and the second edge, respectively, of the control gate.  
   
   
       22 . The method of  claim 20  wherein exposing the second portion of the substrate separates the charge trapping layer into a first charge trapping layer and a second charge trapping layer, and wherein the control gate covers a length of at least one of the first or second charge trapping layers that is less than one-half a length of the control gate.  
   
   
       23 . The method of  claim 20  wherein exposing the second portion of the substrate separates the charge trapping layer into a first charge trapping layer and a second charge trapping layer, and wherein the control gate covers a length of at least one of the first or second charge trapping layers that is less than one-third a length of the control gate.  
   
   
       24 . The method of  claim 20  wherein exposing the second portion of the substrate separates the charge trapping layer into a first charge trapping layer and a second charge trapping layer, and wherein the control gate covers a length of at least one of the first or second charge trapping layers that is less than one-fourth a length of the control gate.  
   
   
       25 . A method for forming a non-volatile memory cell, the method comprising: 
 forming a tunneling layer over a first portion, a second portion, and a third portion of a substrate;    forming a charge trapping layer disposed on the tunneling layer;    forming a masking layer on the charge trapping layer;    patterning the masking layer;    using the patterned masking layer as a mask, etching the charge trapping layer and the tunneling layer to expose the second portion of the substrate:    forming a blocking layer disposed on the charge trapping layer over the first and third portions of the substrate;    forming an insulating layer on the second portion of the substrate;    forming a control gate disposed on the insulating layer on the second portion of the substrate and on the blocking layer.    
   
   
       26 . The method of  claim 25  wherein forming an insulating layer on the second portion of the substrate comprises depositing the insulating layer.  
   
   
       27 . The method of  claim 26 , further comprising thermally growing a gate insulating layer on the deposited insulating layer.  
   
   
       28 . The method of  claim 25  wherein forming a blocking layer and forming an insulating layer occur simultaneously.