Apparatus and Method for Supplying Power in Semiconductor Device

Abstract

Provided is directed to an apparatus and method of supplying power in a semiconductor memory device which supplies an external voltage of high level at the beginning operation which current consumption is rapidly increased and then supplies an internal voltage of a target level, but the external voltage is supplied for a longer time in case that the current consumption is increased more when plural pairs of bitlines are selected than when a pair of bitlines is selected, and thus the apparatus comprises the relatively small number of internal voltage generators and also it is capable of improving reliability of a circuit operation.

1 . An apparatus of supplying power in a semiconductor memory device, comprising: 
 an internal voltage generator for generating an internal operation voltage and then outputting it to an output terminal;    a pulse generator for generating a first overdriving signal having a first pulse width in a refresh operation and generating a second overdriving signal having a second pulse width narrower than the first pulse width in a normal mode; and    a switching device for transferring an external power source voltage to the output terminal according to the overdriving signal outputted from the pulse generator.    
   
   
       2 . The apparatus of  claim 1 , wherein the pulse generator generates the first overdriving signal when a refresh operation signal is inputted.  
   
   
       3 . The apparatus of  claim 1 , wherein the pulse generator generates the overdriving signal by an enable signal which becomes high level in response of inputting an active command signal, and outputs the first overdriving signal when a refresh operation signal is inputted.  
   
   
       4 . The apparatus of  claim 1 , wherein the pulse generator includes: 
 a first inverter for inverting a refresh operation signal;    a first pulse generator for generating the first overdriving signal having the first pulse width, according to an output signal of the first inverter and an enable signal; and    a second pulse generator for generating the second overdriving signal having the second pulse width which is narrower than the first pulse width, according to the a refresh operation signal and the enable signal.    
   
   
       5 . The apparatus of  claim 4 , further including: a NAND gate which an output terminal of the first pulse generator and an output terminal of the second pulse generator are connected to its input terminal; and 
 a second inverter for inverting an output signal of the NAND gate.    
   
   
       6 . The apparatus of  claim 4 , wherein the first pulse generator includes: a first reverse delay unit for inverting and delaying the enable signal; and a second NAND gate which the enable signal, an output signal of the first reverse delay unit, and an output signal of the first inverter are inputted.  
   
   
       7 . The apparatus of  claim 6 , wherein the first reverse delay unit delays the enable signal as wide as the first pulse width.  
   
   
       8 . The apparatus of  claim 4 , wherein the second pulse generator includes: a second reverse delay unit for inverting and delaying the enable signal; a third NAND gate which the enable signal, an output signal of the second reverse delay unit, and the refresh operation signal are inputted.  
   
   
       9 . The apparatus of  claim 8 , wherein the second reverse delay unit delays the enable signal as wide as the second pulse width.  
   
   
       10 . The apparatus of  claim 1 , wherein the switching device includes a PMOS transistor.  
   
   
       11 . A method of supplying power in the semiconductor memory device, comprising steps of: 
 supplying an external voltage to a circuit for a first predetermined supplying time at the beginning of a normal mode, wherein the external voltage is supplied to the circuit for a second predetermined supplying time longer than the first predetermined supplying time at the beginning of a refresh operation; and    supplying an internal voltage lower than the external voltage to the circuit after the first predetermined supplying time or the second predetermined supplying time.    
   
   
       12 . An apparatus of supplying power in a semiconductor memory device, comprising: 
 an internal voltage generator for generating an internal operation voltage and then outputting the internal operation voltage to an output terminal;    a switching connected between an external power source voltage terminal and the output terminal, and operated by a first overdriving signal or a second overdriving signal; and    a pulse generator for outputting the first overdriving signal so as to supply an external power source voltage to the output terminal for a long time at the beginning of a refresh operation, and outputting the second overdriving signal so as to supply the external power source voltage to the output terminal for a short time at the beginning of a normal mode.    
   
   
       13 . The apparatus of  claim 12 , wherein the pulse generator generates the overdriving signals in response to an enable signal, and outputs the first overdriving signal when a refresh operation signal is inputted.  
   
   
       14 . The apparatus of  claim 12 , wherein the pulse generator includes: 
 a first inverter for inverting a refresh operation signal;    a first pulse generator for generating the first overdriving signal having a first pulse width, according to an output signal of the first inverter and an enable signal; and    a second pulse generator for generating the second overdriving signal having a second pulse width which is narrower than the first pulse width, according to the refresh operation signal and the enable signal.