US2008017976A1PendingUtilityA1

Capillary underfill and mold encapsulation method and apparatus

Assignee: INTEL CORPPriority: Sep 30, 2003Filed: Aug 8, 2007Published: Jan 24, 2008
Est. expirySep 30, 2023(expired)· nominal 20-yr term from priority
H10W 72/856H10W 74/15H10W 90/734H10W 90/724H10W 74/114H10W 74/012
40
PatentIndex Score
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Claims

Abstract

A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.

Claims

exact text as granted — not AI-modified
1 . A semiconductor package comprising: 
 a substrate;    a die attached to the substrate;    an underfill material positioned between the die and the substrate;    a molding material in contact with at least a portion of the substrate and the die.    
   
   
       2 . The semiconductor package of  claim 1  wherein the underfill material positioned between the die and the substrate is different than the molding material.  
   
   
       3 . The semiconductor package of  claim 1  wherein the die includes: 
 a frontside surface near the substrate;    a backside surface; and    four sidewall surfaces, wherein the molding material contacts the four sidewall surfaces.    
   
   
       4 . The semiconductor package of  claim 1  wherein the die includes: 
 a frontside surface near the substrate;    a backside surface; and    four sidewall surfaces, wherein the molding material contacts the four sidewall surfaces and the backside surface is devoid of the molding material.    
   
   
       5 . The semiconductor package of  claim 1  wherein the die includes: 
 a frontside surface near the substrate;    a backside surface; and    four sidewall surfaces, wherein the molding material contacts the four sidewall surfaces and the backside surface.    
   
   
       6 . A system comprising: 
 a semiconductor package including: 
 a substrate;  
 a die attached to the substrate;  
 an underfill material positioned between the die and the substrate; and  
 a molding material in contact with at least a portion of the substrate and the die; and  
 a heat sink in thermal contact with the semiconductor package.  
   
   
   
       7 . The system of  claim 6  wherein the semiconductor package includes: 
 a backside surface; and    four sidewall surfaces, wherein the molding material contacts the four sidewall surfaces and the backside surface.    
   
   
       8 . The system of  claim 6  wherein the semiconductor package includes: 
 a backside surface; and    four sidewall surfaces, wherein the molding material contacts the four sidewall surfaces and the backside surface is devoid of the molding material and wherein the heat sink is attached to the backside surface of the die.    
   
   
       9 . The system of  claim 8  further comprising a thermally conductive material located between the backside surface of the die and the heat sink.  
   
   
       10 . The system of  claim 6  further comprising a printed circuit board wherein the semiconductor package is attached to the printed circuit board.  
   
   
       11 . The system of  claim 6  wherein the die of the semiconductor package is a microprocessor.

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