Memory cell and fabricating method thereof

Abstract

A fabricating method of a memory cell including the following steps is provided. First, a poly-Si island including a source doped region, a drain doped region, and a channel region located therebetween is formed on a substrate. Then, a dielectric layer is formed on the poly-Si island. Afterward, an amorphous silicon-germanium (α-SiGe) layer is formed on the dielectric layer. Next, a laser annealing process is performed to oxidize the α-SiGe layer into a silicon oxide layer, so as to separate out Ge atoms from the α-SiGe layer to form a Ge quantum dot layer between the silicon oxide layer and the dielectric layer. After that, a control gate is formed on the silicon oxide layer.

What is claimed is: 
     
         1 . A method of fabricating a memory cell, comprising:
 forming a poly-Si island on a substrate, wherein the poly-Si island comprises a source doped region, a drain doped region, and a channel region located therebetween;   forming a first dielectric layer on the poly-Si island;   forming an α-SiGe layer on the first dielectric layer;   performing a laser annealing process to oxidize the α-SiGe layer into a silicon oxide layer, so as to separate out Ge atoms from the α-SiGe layer to form a Ge quantum dot layer between the silicon oxide layer and the first dielectric layer; and   forming a control gate on the silicon oxide layer.   
     
     
         2 . The method of fabricating the memory cell as claimed in  claim 1 , wherein the laser annealing process comprises an excimer laser annealing process. 
     
     
         3 . The method of fabricating the memory cell as claimed in  claim 1 , wherein the laser annealing process is performed in an atmosphere containing oxygen. 
     
     
         4 . The method of fabricating the memory cell as claimed in  claim 1 , wherein a material of the silicon oxide layer comprises silicon dioxide. 
     
     
         5 . The method of fabricating the memory cell as claimed in  claim 1 , wherein the thickness of the α-SiGe layer is in a range of about  3 - 10  nm. 
     
     
         6 . The method of fabricating the memory cell as claimed in  claim 1 , wherein the method of forming the poly-Si island comprises:
 forming an amorphous silicon layer on the substrate;   performing an annealing process to recrystallize the amorphous silicon layer into a polysilicon layer;   patterning the polysilicon layer; and   doping the polysilicon layer to form the source doped region, the drain doped region, and the channel region.   
     
     
         7 . The method of fabricating the memory cell as claimed in  claim 6 , wherein the annealing process comprises an excimer laser annealing process. 
     
     
         8 . The method of fabricating the memory cell as claimed in  claim 1 , further comprising forming a buffer layer between the substrate and the poly-Si island. 
     
     
         9 . The method of fabricating the memory cell as claimed in  claim 1 , wherein a material of the first dielectric layer comprises silicon dioxide. 
     
     
         10 . The method of fabricating the memory cell as claimed in  claim 1 , further comprising forming a second dielectric layer between the silicon oxide layer and the control gate. 
     
     
         11 . The method of fabricating the memory cell as claimed in  claim 10 , wherein a material of the second dielectric layer comprises silicon dioxide. 
     
     
         12 . A method of fabricating a memory cell, comprising:
 providing a substrate;   forming a control gate on the substrate;   forming a dielectric layer to cover the control gate and the substrate;   forming an α-SiGe layer on the dielectric layer;   performing a laser annealing process to oxidize the α-SiGe layer into a silicon oxide layer, so as to separate out Ge atoms from the α-SiGe layer to form a Ge quantum dot layer between the silicon oxide layer and the dielectric layer; and   forming a poly-Si island on the silicon oxide layer, wherein the poly-Si island comprises a source doped region, a drain doped region, and a channel region located therebetween.   
     
     
         13 . The method of fabricating the memory cell as claimed in  claim 12 , wherein the laser annealing process comprises an excimer laser annealing process. 
     
     
         14 . The method of fabricating the memory cell as claimed in  claim 12 , wherein the laser annealing process is performed in an atmosphere containing oxygen. 
     
     
         15 . The method of fabricating the memory cell as claimed in  claim 12 , wherein a material of the silicon oxide layer comprises silicon dioxide. 
     
     
         16 . The method of fabricating the memory cell as claimed in  claim 12 , wherein the thickness of the α-SiGe layer is in a range of about  3 - 10  nm. 
     
     
         17 . The method of fabricating the memory cell as claimed in  claim 12 , wherein the method of forming the poly-Si island comprises:
 forming an amorphous silicon layer on the silicon oxide layer;   performing an annealing process to recrystallize the amorphous silicon layer into a polysilicon layer;   patterning the polysilicon layer; and   doping the polysilicon layer to form the source doped region, the drain doped region, and the channel region.   
     
     
         18 . The method of fabricating the memory cell as claimed in  claim 17 , wherein the annealing process comprises an ELA process. 
     
     
         19 . The method of fabricating the memory cell as claimed in  claim 12 , further comprising forming a buffer layer between the substrate and the control gate. 
     
     
         20 . The method of fabricating the memory cell as claimed in  claim 12 , wherein a material of the dielectric layer comprises silicon dioxide. 
     
     
         21 . A memory cell, suitable to be disposed on a substrate, the memory cell comprising:
 a poly-Si island, disposed on the substrate, wherein the poly-Si island comprises a source doped region, a drain doped region, and a channel region located therebetween;   a first dielectric layer, disposed on the poly-Si island;   a Ge quantum dot layer, disposed on the first dielectric layer;   a silicon oxide layer, disposed on the Ge quantum dot layer; and   a control gate, disposed on the silicon oxide layer.   
     
     
         22 . The memory cell as claimed in  claim 21 , wherein a material of the silicon oxide layer comprises silicon dioxide. 
     
     
         23 . The memory cell as claimed in  claim 21 , wherein a material of the first dielectric layer comprises silicon dioxide. 
     
     
         24 . The memory cell as claimed in  claim 21 , further comprising a second dielectric layer disposed between the silicon oxide layer and the control gate. 
     
     
         25 . The memory cell as claimed in  claim 24 , wherein a material of the second dielectric layer comprises silicon dioxide. 
     
     
         26 . The memory cell as claimed in  claim 21 , further comprising a buffer layer disposed between the substrate and the poly-Si island. 
     
     
         27 . A memory cell, suitable to be disposed on a substrate, the memory cell comprising:
 a control gate, disposed on the substrate;   a dielectric layer, disposed on the control gate, and located on the substrate;   a Ge quantum dot layer, disposed on the dielectric layer;   a silicon oxide layer, disposed on the Ge quantum dot layer; and   a poly-Si island, disposed on the silicon oxide layer, wherein the poly-Si island comprises a source doped region, a drain doped region, and a channel region located therebetween.   
     
     
         28 . The memory cell as claimed in  claim 27 , wherein a material of the silicon oxide layer comprises silicon dioxide. 
     
     
         29 . The memory cell as claimed in  claim 27 , wherein a material of the dielectric layer comprises silicon dioxide. 
     
     
         30 . The memory cell as claimed in  claim 27 , further comprising a buffer layer disposed between the substrate and the control gate.