US2008017407A1PendingUtilityA1
Interposer and electronic device using the same
Est. expiryJul 24, 2026(expired)· nominal 20-yr term from priority
Inventors:Shuichi Kawano
H05K 2201/10674H05K 1/112H05K 1/0306H05K 3/4608H05K 2201/09309H05K 1/162H10W 90/724H10W 90/701H10W 72/9415H10W 72/9226H10W 72/952H10W 72/923H10W 72/244H10W 72/90H10W 70/635H10W 72/00H10W 70/698H10W 70/60H10D 84/00
50
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A novel interposer( 10 ) includes a silicon substrate( 12 ), a plurality of through-hole conductors ( 20 ) formed on the silicon substrate, and capacitors ( 15 ) having of upper and lower electrodes ( 14,18 ) formed with land portions, respectively, of the through-hole conductors, and a dielectric layer ( 16 ) formed between both the electrodes. When desired, wiring pattern layers can be formed on a layer separate from the capacitors.
Claims
exact text as granted — not AI-modified1 . An interposer comprising a capacitor formed on a generally entire surface of a substrate.
2 . The interposer according to claim 1 , comprising:
the substrate including a plurality of through-hole conductors; some of the through hole conductors that have land portions formed with an upper electrode of the capacitors; some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and a dielectric layer interposed between the upper electrodes and the lower electrodes.
3 . The interposer according to claim 2 , wherein
some of the through-hole conductors are formed as through-hole conductors for signal on a central portion of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed surrounding the through-hole conductors for signal.
4 . The interposer according to claim 2 , wherein
some of the through-hole conductors are formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed inside of the peripheral region of the surface of the substrate.
5 . The interposer according to claim 1 or 2 , further comprising a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
6 . The interposer according to claim 1 or 2 , wherein the substrate is a silicon substrate.
7 . The interposer according to claim 1 or 2 , wherein the through-hole conductors are made of copper.
8 . The interposer according to claim 1 or 2 , wherein the upper and lower electrodes are made of nickel or platinum.
9 . The interposer according to claim 1 or 2 , wherein the dielectric layer is made of a ferroelectric substance.
10 . The interposer according to claim 1 or 2 , wherein the dielectric layer is made of barium titanate.
11 . The interposer according to claim 1 or 2 , wherein at least one surface of the interposer is covered with a solder resist layer or an insulating resin layer.
12 . An electronic device comprising
an IC chip; a package substrate; and an interposer, according to claim 1 or 2 , interposed between the IC chip and the package substrate and electrically connected to the both, wherein the interposer provides capacitors.Join the waitlist — get patent alerts
Track US2008017407A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.