Semiconductor memory device and bit error detection method thereof

Abstract

A memory device detects and corrects bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

1 . A semiconductor memory device comprising: 
 a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells; and    an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation,    wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code.    
   
   
       2 . The semiconductor memory device as set forth in  claim 1 , wherein the CRC circuit generates a pass signal when the read CRC code matches the write CRC code and generates a fail signal when the read CRC code does not match the write CRC code.  
   
   
       3 . The semiconductor memory device as set forth in  claim 1 , wherein the CRC circuit comprises: 
 a CRC engine receiving the data corrected by the ECC circuit and generating the read CRC code; and    a comparator generating the pass signal when the read CRC code matches with the write CRC code, and generating the fail signal when the read CRC code does not match the write CRC code.    
   
   
       4 . The semiconductor memory device as set forth in  claim 1 , wherein the semiconductor memory device is a NAND flash memory device comprising a cell array divided into main and spare regions, and 
 wherein the data is programmed into the main region and the ECC and CRC codes are programmed into the spare region.    
   
   
       5 . The semiconductor memory device as set forth in  claim 4 , wherein the ECC circuit detects two error bits and corrects one error bit, and 
 wherein the CRC circuit detects more than two error bits.    
   
   
       6 . A semiconductor memory device comprising: 
 a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells;    a first error correction code (ECC) circuit generating a first ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the first ECC code during a read operation; and    a second ECC circuit generating a second ECC code corresponding to the write CRC data and detecting and correcting a bit error of the write CRC code by means of the second ECC code during the read operation,    wherein the CRC circuit generates a read CRC code corresponding to data corrected by the first ECC circuit during the read operation, and corrects a bit error of the data according to a comparison of the read CRC code and the write CRC code corrected by the second ECC circuit.    
   
   
       7 . The semiconductor memory device as set forth in  claim 6 , wherein the CRC circuit generates a pass signal when the read CRC code matches the corrected write CRC code, and generates a fail signal when the read CRC code does not match the corrected write CRC code.  
   
   
       8 . The semiconductor memory device as set forth in  claim 6 , wherein the CRC circuit comprises: 
 a CRC engine receiving the data corrected by the first ECC circuit and generating the read CRC code; and    a comparator generating the pass signal when the read CRC code matches the corrected write CRC code, and generating the fail signal when the read CRC code does not match the corrected write CRC code.    
   
   
       9 . The semiconductor memory device as set forth in  claim 6 , wherein the semiconductor memory device is a NAND flash memory device that has a cell array divided into main and spare regions, and 
 wherein the data is programmed into the main region and the first and second ECC codes and the CRC code are programmed into the spare region.:    
   
   
       10 . The semiconductor memory device as set forth in  claim 9 , wherein the first and second ECC circuits each detect two error bits and correct one error bit, and 
 wherein the CRC circuit detects more than two error bits.    
   
   
       11 . The semiconductor memory device as set forth in  claim 9 , wherein the data, the first and second ECC codes, and the CRC code are programmed substantially simultaneously.  
   
   
       12 . A method of detecting a bit error in a semiconductor memory device, comprising: 
 generating error correction code (ECC) and cyclic redundancy check (CRC) codes corresponding to data to be stored in memory cells;    storing the data in the memory cells;    correcting a bit error for the data stored in the memory cells by means of the ECC code;    generating a read CRC code corresponding to the data corrected with the bit error; and    detecting a bit error of the data according to a comparison of the read CRC code to the write CRC code.    
   
   
       13 . The method as set forth in  claim 12 , wherein correcting the bit error comprises treating the data as being failed when the number of error bits is over a correctable number of error bits.  
   
   
       14 . The method as set forth in  claim 12 , further comprising determining a failure of the data when the read CRC code does not match the write CRC code.  
   
   
       15 . The method as set forth in  claim 12 , wherein the semiconductor memory device is a NAND flash memory device comprising a cell array divided into main and spare regions, 
 the method further comprising programming the data into the main region and programming the ECC and CRC codes into the spare region.    
   
   
       16 . The method as set forth in  claim 15 , wherein correcting the bit error comprises detecting two error bits and correcting one error bit, and 
 wherein detecting the bit error of the data comprises determining a bit error in a corrected bit error.    
   
   
       17 . A method of detecting a bit error in a semiconductor memory device, comprising: 
 generating a write cyclic redundancy check (CRC) code corresponding to data to be stored in memory cells;    generating a first error correction code (ECC) code corresponding to the data to be stored in the memory cells, and a second ECC code corresponding to the write CRC code;    programming the data, the write CRC code, and the first and second ECC codes into the memory cells;    correcting a bit error of the data by means of the first ECC code, and a bit error of the write CRC code by means of the second ECC code;    generating a read CRC code corresponding to the data corrected with the bit error; and    detecting a bit error of the data according to a comparison of the read CRC code and the write CRC code corrected with the bit error.    
   
   
       18 . The method as set forth in  claim 17 , wherein correcting the bit error further comprises treating the data as being failed when the number of error bits is over a correctable number of error bits.  
   
   
       19 . The method as set forth in  claim 17 , wherein the semiconductor memory device is a NAND flash memory device comprising a cell array divided into main and spare regions, and 
 the method further comprising programmed the data into the main region, and the first ECC codes, the second ECC codes, and the CRC code are programmed into the spare region.    
   
   
       20 . The method as set forth in  claim 19 , wherein correcting the bit error comprises detecting two error bits and correcting one error bit, and 
 wherein detecting the bit error of the data further comprises determining a bit error in a corrected bit error.